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51. 发明授权

US08578387B1 Dynamic load balancing of instructions for execution by heterogeneous processing engines 有权
标题翻译：用于异构处理引擎执行的指令的动态负载平衡
公开(公告)号：US08578387B1
公开(公告)日：2013-11-05
申请号：US11831873
申请日：2007-07-31
申请人： Peter C. Mills , Stuart F. Oberman , John Erik Lindholm , Samuel Liu
发明人： Peter C. Mills , Stuart F. Oberman , John Erik Lindholm , Samuel Liu
IPC分类号： G06F9/46
CPC分类号： G06F9/5044 , G06F9/3836 , G06F9/3851 , G06F9/3887 , G06F2209/507 , Y02D10/22
摘要： An embodiment of a computing system is configured to process data using a multithreaded SIMD architecture that includes heterogeneous processing engines to execute a program. The program is constructed of various program instructions. A first type of the program instructions can only be executed by a first type of processing engine and a third type of program instructions can only be executed by a second type of processing engine. A second type of program instructions can be executed by the first and the second type of processing engines. An assignment unit may be configured to dynamically determine which of the two processing engines executes any program instructions of the second type in order to balance the workload between the heterogeneous processing engines.
摘要翻译：计算系统的实施例被配置为使用包括异构处理引擎来执行程序的多线程SIMD架构来处理数据。该程序由各种程序指令构成。第一类型的程序指令只能由第一类型的处理引擎执行，并且第三类型的程序指令只能由第二类型的处理引擎执行。第二类型的程序指令可以由第一类和第二类处理引擎执行。分配单元可以被配置为动态地确定两个处理引擎中的哪一个执行第二类型的任何程序指令，以便平衡异构处理引擎之间的工作负载。

52. 发明申请

US20120218267A1 PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROGRAMS 有权
标题翻译：可编程图形处理程序，用于多方案执行程序
公开(公告)号：US20120218267A1
公开(公告)日：2012-08-30
申请号：US13466043
申请日：2012-05-07
申请人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
发明人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
IPC分类号： G06T17/20 , G06T1/20 , G06T1/00
CPC分类号： G06T15/005
摘要： A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
摘要翻译：处理单元包括多个执行流水线，每个执行流水线连接到第一输入部分，用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和用于存储经处理的顶点数据的第二输出部分。经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。经处理的像素数据被输出到光栅分析器。

53. 发明申请

US20110252204A1 SHARED SINGLE ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL REQUESTS 有权
标题翻译：具有多个并行请求管理的共享单个访问记忆
公开(公告)号：US20110252204A1
公开(公告)日：2011-10-13
申请号：US13165638
申请日：2011-06-21
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , Y02D10/13
摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
摘要翻译：多线程处理器中的并发线程使用内存。任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。允许所有这些请求并行进行，而其他请求被推迟。可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

54. 发明申请

US20110072244A1 Credit-Based Streaming Multiprocessor Warp Scheduling 有权
标题翻译：基于信用流的多处理器整流器调度
公开(公告)号：US20110072244A1
公开(公告)日：2011-03-24
申请号：US12885299
申请日：2010-09-17
申请人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
发明人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution.
摘要翻译：本发明的一个实施例提出了一种用于确保高速缓存访问指令被调度用于在多线程系统中执行以提高高速缓存位置和系统性能的技术。可以使用基于信用的技术来对组中的每个翘曲的指令调度来控制指令，使得一组经线被均匀地处理。对每个经纱计算信用额度，并且信用额度有助于每个经线的权重。权重用于选择要执行的经线的指令。

55. 发明授权

US07640285B1 Multipurpose arithmetic functional unit 有权
标题翻译：多功能算术功能单元
公开(公告)号：US07640285B1
公开(公告)日：2009-12-29
申请号：US10970101
申请日：2004-10-20
申请人： Stuart F. Oberman , Ming Y. Siu
发明人： Stuart F. Oberman , Ming Y. Siu
IPC分类号： G06F7/38 , G06G1/02
CPC分类号： G06F7/57 , G06F2207/3884
摘要： Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x−xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.
摘要翻译：多用途算术功能单元可以执行平面属性插值和一元函数近似运算。在一个实施例中，通过计算A * x + B * y + C来执行坐标（x，y）的平面内插操作，并且通过计算F2（xb）* xh2 + F1（xb）来执行操作数x的一元函数近似运算）* xh + F0（xb），其中xh = x-xb。共享乘法器和加法器电路有利地用于实现两类操作的乘积和求和运算。

56. 发明授权

US07634637B1 Execution of parallel groups of threads with per-instruction serialization 有权
标题翻译：使用每条指令序列化执行并行组线程
公开(公告)号：US07634637B1
公开(公告)日：2009-12-15
申请号：US11305803
申请日：2005-12-16
申请人： John Erik Lindholm , Stuart F. Oberman
发明人： John Erik Lindholm , Stuart F. Oberman
IPC分类号： G06F15/76 , G06F9/00
CPC分类号： G06F9/3851 , G06F9/3853 , G06F9/3879 , G06F9/3885 , G06F9/3887 , G06F9/3891
摘要： In a processor, a SIMD group (a group of threads for which instructions are issued in parallel using single instruction, multiple data instruction issue techniques) is logically divided into two or more “SIMD subsets,” each containing one or more of the threads in the SIMD group. Each SIMD subset is associated with a different instance of a variable state parameter. The processor determines which of the instructions to be executed for the SIMD group rely on the state variable and serializes execution of such instructions so that the instruction is executed separately for each SIMD subset. Instructions that do not rely on the state variable are advantageously not serialized.
摘要翻译：在处理器中，SIMD组（一组线程，其中使用单个指令并行地发出指令，多个数据指令发布技术）在逻辑上被划分为两个或更多个“SIMD子集”，每个包含一个或多个线程 SIMD组。每个SIMD子集与可变状态参数的不同实例相关联。处理器确定要为SIMD组执行的指令中的哪一个依赖于状态变量并串行化这些指令的执行，使得针对每个SIMD子集分别执行该指令。不依赖于状态变量的指令有利地不是序列化的。

57. 发明授权

US07428566B2 Multipurpose functional unit with multiply-add and format conversion pipeline 有权
标题翻译：具有多重加法和格式转换管道的多用途功能单元
公开(公告)号：US07428566B2
公开(公告)日：2008-09-23
申请号：US10985674
申请日：2004-11-10
申请人： Ming Y. Siu , Stuart F. Oberman
发明人： Ming Y. Siu , Stuart F. Oberman
IPC分类号： G06F7/38
CPC分类号： G06F9/30014 , G06F9/3885
摘要： A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and logical test operations.
摘要翻译：多用途功能单元可配置为支持多种操作，包括乘法加法和格式转换操作，以及其他整数和/或浮点算术运算，布尔运算和逻辑运算。

58. 发明授权

US07406041B2 System and method for late-dropping packets in a network switch 失效
标题翻译：在网络交换机中丢包的系统和方法
公开(公告)号：US07406041B2
公开(公告)日：2008-07-29
申请号：US10209545
申请日：2002-07-31
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04L12/26
CPC分类号： H04L47/30 , H04L47/10 , H04L47/2441 , H04L47/31 , H04L47/32 , H04L49/50
摘要： A system and method for late-dropping packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the switch may be subject to input thresholding, and may be assigned to a flow within a group. A portion of a packet subject to input thresholding may be accepted into the switch and assigned to a group and flow even if, at the time of arrival of the portion, there are not enough resources available to receive the remainder of the packet. This partial receipt of the packet is allowed because of the possibility of additional resources becoming available between the time of receipt of and resource allocation for the portion of the packet and receipt of subsequent portions of the packet.
摘要翻译：一种用于在网络交换机中后期丢包的系统和方法。网络交换机可以包括多个输入端口，多个输出端口以及通过数据传输逻辑耦合到输入端口和输出端口的共享随机存取存储器。进入交换机的数据包可能需要输入阈值，并且可以分配给组内的流。即使在部分到达时，没有足够的资源可用于接收分组的其余部分，经过输入阈值处理的分组的一部分也可被接收到交换机中并分配给组和流。允许分组的这种部分接收是因为在分组的接收时间和分组的部分和分组的后续部分的接收之间有额外的资源可用。

59. 发明申请

US20080109611A1 OPERAND COLLECTOR ARCHITECTURE 有权
标题翻译：操作收集架构
公开(公告)号：US20080109611A1
公开(公告)日：2008-05-08
申请号：US11555649
申请日：2006-11-01
申请人： Samuel Liu , John Erik Lindholm , Ming Y. Siu , Brett W. Coon , Stuart F. Oberman
发明人： Samuel Liu , John Erik Lindholm , Ming Y. Siu , Brett W. Coon , Stuart F. Oberman
IPC分类号： G06F13/00
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30167 , G06F9/3824 , G06F9/3851 , G06F9/3885
摘要： An apparatus and method for simulating a multi-ported memory using lower port count memories as banks. A collector units gather source operands from the banks as needed to process program instructions. The collector units also gather constants that are used as operands. When all of the source operands needed to process a program instruction have been gathered, a collector unit outputs the source operands to an execution unit while avoiding writeback conflicts to registers specified by the program instruction that may be accessed by other execution units.
摘要翻译：一种使用较低端口计数存储器作为存储体来模拟多端口存储器的装置和方法。收集器单元根据需要从银行收集源操作数，以处理程序指令。收集器单元还收集用作操作数的常量。当收集处理程序指令所需的所有源操作数时，收集器单元将源操作数输出到执行单元，同时避免与由其他执行单元访问的程序指令指定的寄存器的写回冲突。

60. 发明授权

US07366745B1 High-speed function approximation 有权
标题翻译：高速函数近似
公开(公告)号：US07366745B1
公开(公告)日：2008-04-29
申请号：US10861184
申请日：2004-06-03
申请人： Stuart F. Oberman , Ming Y. Siu
发明人： Stuart F. Oberman , Ming Y. Siu
IPC分类号： G06F1/02
CPC分类号： G06F7/544
摘要： Methods and apparatuses are presented for determining coefficients for a polynomial-based approximation of a function, by iteratively estimating a first coefficient, reducing the first coefficient to a lower precision to obtain a first limited-precision coefficient, analytically calculating a second coefficient by taking into account the first limited-precision coefficient, reducing the second coefficient to a lower precision to obtain a second limited-precision coefficient, iteratively estimating a third coefficient by taking into account at least one of the first limited-precision coefficient and the second limited-precision coefficient, and reducing the third coefficient to a lower precision to obtain a third limited-precision coefficient. In one embodiment of the invention, the polynomial-based approximation relates to a minimax approximation of the function approximated, and at least one of the steps for iteratively estimating the first coefficient and iteratively estimating the third coefficient involves use of a Remez exchange algorithm.
摘要翻译：提出方法和装置，用于通过迭代地估计第一系数来确定函数的基于多项式的近似的系数，将第一系数降低到较低的精度以获得第一有限精度系数，通过考虑计算第二系数来分析计算第二系数考虑到第一有限精度系数，将第二系数降低到较低精度以获得第二有限精度系数，通过考虑第一有限精度系数和第二限制精度系数中的至少一个来迭代地估计第三系数系数，并将第三系数降低到较低的精度，以获得第三有限精度系数。在本发明的一个实施例中，基于多项式的近似涉及逼近的函数的最小近似，并且用于迭代地估计第一系数并迭代地估计第三系数的步骤中的至少一个涉及使用Remez交换算法。

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