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51. 发明授权

US08674447B2 Transistor with improved sigma-shaped embedded stressor and method of formation 失效
标题翻译：具有改进的σ形嵌入式应力源的晶体管及其形成方法
公开(公告)号：US08674447B2
公开(公告)日：2014-03-18
申请号：US13457980
申请日：2012-04-27
申请人： Thomas N Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/78
CPC分类号： H01L21/02609 , H01L21/265 , H01L21/28026 , H01L21/30608 , H01L21/3065 , H01L21/308 , H01L21/3086 , H01L29/165 , H01L29/66431 , H01L29/6653 , H01L29/66575 , H01L29/66636 , H01L29/7848
摘要： A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.
摘要翻译：具有西格玛通道侧壁和垂直隔离侧壁的半导体晶体管器件中的嵌入式应力源的方法和结构。嵌入的应力器结构由第一蚀刻制成，以在具有栅极和第一和第二间隔物的衬底中形成凹陷。去除第二间隔物，并且第二蚀刻在通道侧壁上的凹部中形成台阶。各向异性蚀刻在凹槽的通道侧壁中产生刻面。小面相遇时，形成顶点。顶点的深度由第二蚀刻深度（阶梯深度）决定。顶点的横向位置由第一间隔件的厚度决定。在凹部中形成具有与衬底不同的晶格间距的半导体材料，以实现嵌入的应力器结构。

52. 发明申请

US20140015014A1 FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES 有权
标题翻译：具有变化阈值电压的场效应晶体管
公开(公告)号：US20140015014A1
公开(公告)日：2014-01-16
申请号：US13545224
申请日：2012-07-10
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
IPC分类号： H01L21/20 , H01L21/336 , H01L29/78
CPC分类号： H01L27/088 , H01L21/02529 , H01L21/02532 , H01L21/0257 , H01L21/02576 , H01L21/02579 , H01L21/28008 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L21/84 , H01L29/167 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/7834 , H01L29/7848
摘要： A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
摘要翻译：一种包括提供包括第一半导体器件和第二半导体器件的半导体衬底的方法，所述第一和第二半导体器件包括虚设衬垫，虚拟栅极和延伸区域; 用掩模保护第二半导体器件; 从第一半导体器件去除虚设间隔物; 以及在所述第一半导体器件的所述延伸区域的顶部上沉积原位掺杂的外延区域。

53. 发明申请

US20140001554A1 SEMICONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE 有权
标题翻译：封闭边缘提供外延源/排水沟的半导体器件
公开(公告)号：US20140001554A1
公开(公告)日：2014-01-02
申请号：US13534407
申请日：2012-06-27
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , G06F17/50 , H01L27/12
CPC分类号： H01L29/0847 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L23/485 , H01L27/1203 , H01L29/0653
摘要： A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.
摘要翻译：形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域涉及对应于第二晶体管的第一晶体管和第二升高区域。第一凸起区域和第二凸起区域由至少一个沟槽电隔离。

54. 发明申请

US20130292766A1 SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES 审中-公开
标题翻译：具有不同阈值电压的晶体管的半导体衬底
公开(公告)号：US20130292766A1
公开(公告)日：2013-11-07
申请号：US13463402
申请日：2012-05-03
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor integrated circuit is provided and includes a first field effect transistor (FET) device and a second FET device formed on a semiconductor substrate. The first FET device has raised source/drain (RSD) structures grown at a first height. The second FET device has RSD structures grown at a second height greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.
摘要翻译：提供了半导体集成电路，并且包括形成在半导体衬底上的第一场效应晶体管（FET）器件和第二FET器件。第一FET器件提高了在第一高度生长的源极/漏极（RSD）结构。第二FET器件具有在大于第一高度的第二高度处生长的RSD结构，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

55. 发明申请

US20130193492A1 SILICON CARBON FILM STRUCTURE AND METHOD 审中-公开
标题翻译：硅碳膜结构与方法
公开(公告)号：US20130193492A1
公开(公告)日：2013-08-01
申请号：US13360823
申请日：2012-01-30
申请人： THOMAS N. ADAM , Kangguo Cheng , Hong He , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
发明人： THOMAS N. ADAM , Kangguo Cheng , Hong He , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/02447 , H01L21/02507 , H01L21/02529 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/7848
摘要： An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors.
摘要翻译：公开了一种改进的硅碳膜结构。膜结构包括多层硅碳和硅。多层形成具有增加的取代碳含量的应力膜结构，并且用于诱导改善某些类型的场效应晶体管的载流子迁移率的应力。

56. 发明申请

US20130126944A1 HETEROJUNCTION BIPOLAR TRANSISTOR WITH EPITAXIAL EMITTER STACK TO IMPROVE VERTICAL SCALING 有权
标题翻译：具有外延发射体堆叠的异相双极晶体管以改善垂直刻度
公开(公告)号：US20130126944A1
公开(公告)日：2013-05-23
申请号：US13303248
申请日：2011-11-23
申请人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
发明人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
IPC分类号： H01L29/70 , H01L21/331
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02439 , H01L21/02447 , H01L21/0245 , H01L21/02521 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L29/0817 , H01L29/1004 , H01L29/41708 , H01L29/66242 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.
摘要翻译：异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。

57. 发明授权

US08361859B2 Stressed transistor with improved metastability 有权
标题翻译：具有改善的亚稳态的强调晶体管
公开(公告)号：US08361859B2
公开(公告)日：2013-01-29
申请号：US12942289
申请日：2010-11-09
申请人： Thomas N. Adam , Stephen W. Bedell , Abhishek Dube , Eric C. T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
发明人： Thomas N. Adam , Stephen W. Bedell , Abhishek Dube , Eric C. T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L21/8238
CPC分类号： H01L29/78 , H01L21/28525 , H01L21/76805 , H01L21/76877 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
摘要翻译：在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。

58. 发明申请

US20120252216A1 Low-Temperature in-situ Removal of Oxide from a Silicon Surface During CMOS Epitaxial Processing 失效
标题翻译： CMOS外延处理期间从硅表面低温原位去除氧化物
公开(公告)号：US20120252216A1
公开(公告)日：2012-10-04
申请号：US13075657
申请日：2011-03-30
申请人： Thomas N. Adam , Stephen W. Bedell , Alexander Reznicek , Devendra K. Sadana
发明人： Thomas N. Adam , Stephen W. Bedell , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L21/302
CPC分类号： H01L21/02046
摘要： Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.
摘要翻译：提供低温原位技术用于在CMOS外延处理期间从硅表面去除氧化物。通过在硅表面上沉积SiGe层，从具有硅表面的半导体晶片去除氧化物; 在低于700℃（以上，例如约450℃）的温度下，从硅表面蚀刻SiGe层; 并重复沉积和蚀刻步骤多次，直到污染物基本上从硅表面除去。在一个变型中，沉积层包括IV族半导体材料和/或其合金。

59. 发明申请

US20120104511A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20120104511A1
公开(公告)日：2012-05-03
申请号：US13349203
申请日：2012-01-12
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L27/092
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

60. 发明授权

US08138061B2 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide 有权
标题翻译：使用亲水硅表面的准疏水Si-Si晶片结合和界面结合氧化物的溶解
公开(公告)号：US08138061B2
公开(公告)日：2012-03-20
申请号：US11031165
申请日：2005-01-07
申请人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
发明人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/46
CPC分类号： H01L21/187 , H01L21/76251
摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.
摘要翻译：本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与用疏水性接合实现的特性相当的性质的结合Si-Si界面的方法。约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

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