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51. 发明授权

US06663723B1 Vapor drying for cleaning photoresists 失效
标题翻译：用于清洁光致抗蚀剂的蒸气干燥
公开(公告)号：US06663723B1
公开(公告)日：2003-12-16
申请号：US09974276
申请日：2001-10-10
申请人： Michael K. Templeton , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan
发明人： Michael K. Templeton , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan
IPC分类号： B08B500
CPC分类号： G03F7/40 , B08B7/00
摘要： One aspect of the present invention relates to a method of cleaning a patterned photoresist clad structure involving the steps of contacting the patterned photoresist clad structure with an alcohol vapor comprising at least one compound having the Formula ROH, wherein R is a hydrocarbon group comprising from 4 to about 8 carbon atoms; condensing the alcohol vapor on the patterned photoresist clad structure; and removing the condensed alcohol vapor from the patterned photoresist clad structure. Another aspect of the present invention involves the use of an alcohol vapor having a boiling point from about 102° C. to about 175° C. Yet another aspect of the present invention involves the use of an alcohol vapor having a flash point from about 15° C. to about 80° C.
摘要翻译：本发明的一个方面涉及一种清洁图案化光致抗蚀剂包覆结构的方法，该方法包括以下步骤：使图案化的光致抗蚀剂包覆结构与包含至少一种具有式ROH的化合物的醇蒸气接触，其中R是包含4 至约8个碳原子; 在图案化的光致抗蚀剂包层结构上冷凝酒精蒸气; 并从图案化的光致抗蚀剂包覆结构去除冷凝的醇蒸气。本发明的另一方面涉及使用沸点为约102℃至约175℃的醇蒸气。本发明的另一方面涉及使用闪点为约15℃的醇蒸汽 ℃至约80℃

52. 发明授权

US06634805B1 Parallel plate development 失效
标题翻译：平行板开发
公开(公告)号：US06634805B1
公开(公告)日：2003-10-21
申请号：US09974340
申请日：2001-10-10
申请人： Michael K. Templeton , Khoi A. Phan , Bharath Rangarajan , Bryan K. Choo , Ramkumar Subramanian
发明人： Michael K. Templeton , Khoi A. Phan , Bharath Rangarajan , Bryan K. Choo , Ramkumar Subramanian
IPC分类号： G03B500
CPC分类号： H01L21/6715 , G03F7/3021
摘要： A system and method is provided for applying a developer to a photoresist material wafer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a apertures for dispensing developer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap. The developer plate is disposed in very close proximity with respect to the wafer, such that the developer is squeezed between the two plates thereby spreading evenly the developer over the wafer.
摘要翻译：提供了一种将显影剂施加到设置在半导体衬底上的光致抗蚀剂材料晶片的系统和方法。显影剂系统和方法采用具有多个用于分配显影剂的孔的显影剂板。优选地，显影剂板具有与晶片类似的形状的底表面。显影剂板设置在晶片上方并且在施加显影剂的过程中基本上和/或完全地包围晶片的顶表面。在晶片和显影剂板的底表面之间形成小的间隙。晶片和显影剂板形成平行板对，使得间隙可以制得足够小，使得显影剂流体快速填充间隙。显影剂板相对于晶片非常接近地设置，使得显影剂被挤压在两个板之间，从而将显影剂均匀地铺展在晶片上。

53. 发明授权

US07187796B1 Systems and methods that employ exposure compensation to provide uniform CD control on reticle during fabrication 失效
标题翻译：使用曝光补偿的系统和方法在制造过程中对掩模版提供均匀的CD控制
公开(公告)号：US07187796B1
公开(公告)日：2007-03-06
申请号：US10676613
申请日：2003-10-01
申请人： Khoi A. Phan , Ramkumar Subramanian , Bhanwar Singh
发明人： Khoi A. Phan , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： G06K9/00
CPC分类号： B82Y40/00 , B82Y10/00 , G03F1/78 , H01J37/3174
摘要： The present invention relates to monitoring and controlling a reticle fabrication process (e.g. employed with an electron beam lithography process). A typical fabrication process involves discrete stages including exposure, post-exposure bake and development. After fabrication is complete, an inspection can be performed on the reticle to determine whether any parameters during fabrication and/or any data points are outside of acceptable tolerances. The data is collected and fed into an algorithm (e.g. data-mining algorithm) utilized to determine which fabrication parameters need to be modified then sends the data to a control system (e.g. advanced process control) to facilitate needed changes to the fabrication parameters.
摘要翻译：本发明涉及监测和控制掩模版制造工艺（例如采用电子束光刻工艺）。典型的制造过程涉及离散阶段，包括曝光，曝光后烘烤和显影。制造完成后，可以对掩模版进行检查，以确定制造期间和/或任何数据点中的任何参数是否超出可接受的公差。收集数据并将其馈送到用于确定哪些制造参数需要被修改的算法（例如数据挖掘算法）中，然后将数据发送到控制系统（例如高级过程控制），以便于对制造参数的所需改变。

54. 发明授权

US07295288B1 Systems and methods of imprint lithography with adjustable mask 有权
标题翻译：带可调面罩的压印光刻系统和方法
公开(公告)号：US07295288B1
公开(公告)日：2007-11-13
申请号：US11000869
申请日：2004-12-01
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
IPC分类号： G03B27/62 , G03B27/02 , G03B27/20
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： Systems and methodologies are provided that account for surface variations of a wafer by adjusting grating features of an imprint lithography mask. Such adjustment employs piezoelectric elements as part of the mask, which can change dimensions (e.g., a height change) and/or move when subjected to an electric voltage. Accordingly, by regulating the amount of electric voltage applied to the piezoelectric elements a controlled expansion for such elements can be obtained, to accommodate for topography variations of the wafer surface.
摘要翻译：提供了通过调节压印光刻掩模的光栅特征来考虑晶片的表面变化的系统和方法。这种调节使用压电元件作为掩模的一部分，其可以在经受电压时改变尺寸（例如，高度变化）和/或移动。因此，通过调节施加到压电元件的电压量，可以获得这些元件的受控膨胀，以适应晶片表面的形貌变化。

55. 发明授权

US06972201B1 Using scatterometry to detect and control undercut for ARC with developable BARCs 失效
标题翻译：使用散射法检测和控制ARC的可切割BARC的底切
公开(公告)号：US06972201B1
公开(公告)日：2005-12-06
申请号：US10755794
申请日：2004-01-12
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
IPC分类号： G03F7/09 , G03F7/30 , G03F7/38 , H01L21/00 , H01L21/027 , H01L21/66
CPC分类号： G03F7/3028 , G03F7/091 , G03F7/38 , H01L21/0276 , H01L22/12
摘要： Architecture for monitoring a bottom anti-reflective coating (BARC) undercut and residual portions thereof during a development stage using scatterometry. The scatterometry system monitors for BARC undercut and residual BARC material, and if detected, controls the process to minimize such effects in subsequent wafers. If one or more of such effects has exceeded a predetermined limit, the wafer is rerouted for further processing, which can include rework, etch back of the affected layer, or rejection of the wafer, for example.
摘要翻译：用于在使用散射测量的显影阶段期间监测底部抗反射涂层（BARC）底切及其残余部分的结构。散射测量系统监测BARC底切和残留BARC材料，如果检测到，则控制该过程以使后续晶片中的这种影响最小化。如果这种效应中的一个或多个已经超过预定限制，则晶片被重新路由以用于进一步处理，例如，其可以包括返工，受影响层的回蚀或晶片的拒绝。

56. 发明授权

US06613500B1 Reducing resist residue defects in open area on patterned wafer using trim mask 有权
标题翻译：使用修剪掩模减少图案化晶片上的开放区域中的抗蚀剂残留缺陷
公开(公告)号：US06613500B1
公开(公告)日：2003-09-02
申请号：US09824079
申请日：2001-04-02
申请人： Khoi A. Phan , Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Jeff Erhardt
发明人： Khoi A. Phan , Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Jeff Erhardt
IPC分类号： G03F700
CPC分类号： G03F7/70425 , G03F7/2022 , G03F7/203 , G03F7/70466
摘要： One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.
摘要翻译：本发明的一个方面涉及减少晶片结构上的抗蚀剂残留缺陷的方法。该方法包括提供具有光致抗蚀剂的半导体结构，光致抗蚀剂包括开放区域和其上的电路区域; 通过具有第一能量剂量的第一光掩模照射开放区域和电路区域以在光致抗蚀剂中实现成像图案; 通过具有第二能量剂量的第二光掩模照射光致抗蚀剂的开放区域; 并显影光致抗蚀剂。

57. 发明授权

US07289193B1 Frame structure for turbulence control in immersion lithography 失效
标题翻译：浸没光刻中湍流控制的框架结构
公开(公告)号：US07289193B1
公开(公告)日：2007-10-30
申请号：US11000654
申请日：2004-12-01
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
IPC分类号： G03B27/54 , G03B27/42
CPC分类号： G03F7/70341
摘要： Disclosed are systems and methods that employ a structural framework of cell gratings placed on a wafer surface during an immersion lithography process to restrict motion of the immersion fluid. Thus, when the stepper lens comes in contact with the immersion fluid, a typically stable immersion fluid dynamics can be maintained with the cells during the immersion lithography process. In addition, various monitoring and control systems are employed to regulate stability of the immersion fluid.
摘要翻译：公开了在浸没光刻工艺期间采用放置在晶片表面上的单元格栅的结构框架以限制浸没流体的运动的系统和方法。因此，当步进透镜与浸没流体接触时，在浸没光刻工艺期间可以与电池一起保持典型稳定的浸没流体动力学。此外，采用各种监控系统来调节浸液的稳定性。

58. 发明授权

US07109046B1 Surface oxide tabulation and photo process control and cost savings 失效
标题翻译：表面氧化物制图和照相工艺控制和成本节约
公开(公告)号：US07109046B1
公开(公告)日：2006-09-19
申请号：US10768514
申请日：2004-01-30
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
IPC分类号： H01L21/00
CPC分类号： H01L22/12
摘要： The present invention relates generally to semiconductor processing, and more particularly to methods and systems for reducing costs of wafer production by analyzing key aspects of wafer status to determine whether to initiate corrective measures to salvage a wafer at an early stage and before substantial costs are incurred in fabricating a defective wafer. One aspect of the present invention provides for growing an oxide layer on a wafer upon a determination that an oxide layer on the wafer surface is absent or is present but inadequate. Another aspect of the present invention provides for a determination of whether to apply preemptory corrective treatment(s) to a wafer surface based on the presence and/or magnitude of nitrogen signatures in an extant oxide surface layer, which can indicate that an undesirable defect known as “footing” will occur during a post-exposure delay period. Thus, the invention advantageously reduces production costs by facilitating a most correct decision to mitigate the source(s) of potential defects at an early stage and, thus, before substantial costs are incurred in production of the wafer.
摘要翻译：本发明一般涉及半导体处理，更具体地说，涉及通过分析晶片状态的关键方面来降低晶片生产成本的方法和系统，以确定是否启动在早期阶段挽救晶片的纠正措施以及在大量成本产生之前在制造缺陷晶片时。本发明的一个方面提供了在确定晶片表面上的氧化物层不存在或存在但不足的情况下，在晶片上生长氧化物层。本发明的另一方面提供了根据现有氧化物表面层中氮标记的存在和/或大小来确定是否对晶片表面施加抢占式校正处理，其可以指示不期望的缺陷已知因为在曝光后延迟期间将发生“立足”。因此，本发明有利地通过促进最正确的决定来降低生产成本，以在早期阶段减轻潜在缺陷的来源，并且因此在生产晶片之前花费大量成本之前。

59. 发明授权

US07076320B1 Scatterometry monitor in cluster process tool environment for advanced process control (APC) 有权
标题翻译：用于高级过程控制（APC）的集群过程工具环境中的散射测量监视器
公开(公告)号：US07076320B1
公开(公告)日：2006-07-11
申请号：US10838827
申请日：2004-05-04
申请人： Khoi A. Phan , Bhanwar Singh , Ramkumar Subramanian
发明人： Khoi A. Phan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G06F19/00
CPC分类号： H01L21/67253 , G03F7/70525
摘要： Systems and methods that improve process control in semiconductor manufacturing are disclosed. According to an aspect of the invention, conditions in a cluster tool environment and/or a wafer therein can be monitored in-situ via, for example, a scatterometry system, to determine whether parameters associated with wafer production are within control limits. A cluster tool environment can include, for example, a lithography track, a stepper, a plasma etcher, a cleaning tool, a chemical bath, etc. If an out-of-control condition is detected, either associated with a tool in the cluster tool environment or with the wafer itself, compensatory measures can be taken to correct the out-of-control condition. The invention can further employ feedback/feed-forward loop(s) to facilitate compensatory action in order to improve process control.
摘要翻译：公开了改进半导体制造过程控制的系统和方法。根据本发明的一个方面，可以通过例如散射测量系统原地监测集群工具环境和/或其中的晶片中的条件，以确定与晶片生产相关的参数是否处于控制限度内。集群工具环境可以包括例如光刻轨迹，步进器，等离子体蚀刻器，清洁工具，化学浴等。如果检测到失控状态，则与集群中的工具相关联工具环境或晶圆本身，可采取补偿措施来纠正失控状态。本发明可以进一步采用反馈/前馈回路来促进补偿动作，以改善过程控制。

60. 发明授权

US07064846B1 Non-lithographic shrink techniques for improving line edge roughness and using imperfect (but simpler) BARCs 有权
标题翻译：非光刻收缩技术，用于改善线边缘粗糙度并使用不完美（但更简单）的BARC
公开(公告)号：US07064846B1
公开(公告)日：2006-06-20
申请号：US10646190
申请日：2003-08-22
申请人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan , Ramkumar Subramanian
发明人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan , Ramkumar Subramanian
IPC分类号： G01B11/04
CPC分类号： G03F7/40
摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) and/or standing wave expression during pattern line formation in an integrated circuit. Systems and methods are disclosed for retaining a target critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER and/or standing wave expression, wherein the shrink component is employed to heat a particular resist to the glass transition temperature of the resist to effectuate mitigation of LER and/or standing wave expression. Additionally, by heating the resist to its glass transition temperature, the systems and methods of the present invention effectively impede deviation from a desired target critical dimension.
摘要翻译：本发明一般涉及光刻系统和方法，更具体地涉及有助于在集成电路中的图案线形成期间减少线边缘粗糙度（LER）和/或驻波表达的系统和方法。公开了用于保持光致抗蚀剂线的目标临界尺寸（CD）的系统和方法，其包括有助于减轻LER和/或驻波表达的非光刻收缩组分，其中采用收缩组分将特定抗蚀剂加热到玻璃抗蚀剂的转变温度来实现LER和/或驻波表达的缓解。此外，通过将抗蚀剂加热至其玻璃化转变温度，本发明的系统和方法有效地阻止了偏离所需目标临界尺寸。

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