专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20100019382A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100019382A1
公开(公告)日：2010-01-28
申请号：US12478837
申请日：2009-06-05
申请人： Takashi MIWA , Michiaki Sugiyama , Kazumasa Yanagisawa
发明人： Takashi MIWA , Michiaki Sugiyama , Kazumasa Yanagisawa
IPC分类号： H01L23/485 , H01L21/50
CPC分类号： H01L23/49838 , H01L21/563 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48227 , H01L2224/48229 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81801 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/112 , H05K3/4652 , H05K2201/09227 , H05K2201/099 , H05K2201/10734 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small. By so doing, both prevention of a short-circuit and improvement of the layout density of lands are attained at a time.
摘要翻译：提供了允许半导体器件的尺寸减小的技术。在具有倒装芯片接合在布线基板上的半导体芯片的BGA型半导体器件中，半导体芯片的突起电极被耦合到在布线基板的上表面上形成的焊盘。布线基板的上表面的焊盘电连接到形成在布线基板的下表面上的焊球。因此，焊盘包括具有与其耦合的引出线的第一类型的焊盘和没有耦合到其上的导出线，但是具有刚好形成的通孔的第二类型的焊盘。焊盘沿着行的前进方向以等间距排列成六行或更多行。然而，行到行间距不是相等的音高。在可能导致短路的陆地列中，相邻行之间的间距变大，而在难以引起短路的陆地行中，相邻行之间的间距变小。通过这样做，一次可以实现防止短路的改善和布局密度的提高。

52. 发明申请

US20090052238A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090052238A1
公开(公告)日：2009-02-26
申请号：US12258964
申请日：2008-10-27
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C16/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以优先考虑第二非易失性存储器区域，以保证存储器信息的重写操作的次数更多。

53. 发明申请

US20080316800A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080316800A1
公开(公告)日：2008-12-25
申请号：US12222753
申请日：2008-08-15
申请人： Masanao Yamaoka , Kenichi Osada , Kazumasa Yanagisawa
发明人： Masanao Yamaoka , Kenichi Osada , Kazumasa Yanagisawa
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译：当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗同时存储数据增加。因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。

54. 发明申请

US20060031655A1 Computer readable storage medium and semiconductor integrated circuit device 审中-公开
公开(公告)号：US20060031655A1
公开(公告)日：2006-02-09
申请号：US11242854
申请日：2005-10-05
申请人： Kei Kato , Masanao Yamaoka , Keiichi Higeta , Kazumasa Yanagisawa , Shigeru Shimada , Kodo Yamauchi , Yoshihiro Shinozaki , Yasuo Taguchi
发明人： Kei Kato , Masanao Yamaoka , Keiichi Higeta , Kazumasa Yanagisawa , Shigeru Shimada , Kodo Yamauchi , Yoshihiro Shinozaki , Yasuo Taguchi
IPC分类号： G06F12/00
CPC分类号： G11C7/106 , G06F17/5045 , G11C7/10 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C2207/104
摘要： The present invention is directed to facilitate change in the specifications of an interface of a memory IP and to improve reusability of the memory IP. A memory module to be mounted on a system LSI or the like is constructed by a basic array and an interface. The basic array is constructed by direct peripheral circuits and a storage circuit. Library data of the basic array is stored in a storage medium such as a CD-R or a magnetic tape and distributed to the user. The library data includes layout pattern data, a logic simulation model defining the operation of the basic array, LSI pattern information such as a layout, device information such as characteristics of a MOS device and layout rules, interface information such as various signal timings, and device specification data such as terminal information.

55. 发明申请

US20050285659A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050285659A1
公开(公告)日：2005-12-29
申请号：US11202279
申请日：2005-08-12
申请人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
发明人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8234 , H01L27/04 , H01L27/088 , H03K3/356 , H03K5/1534 , H03K19/0175 , H03K19/0185
CPC分类号： H03K5/1534 , H03K3/356113 , H03K19/018521
摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.
摘要翻译：半导体器件包括差分电平转换器电路，其接收第一信号并输出更大振幅的第二信号。差分电平转换器具有用于接收第一信号的第一MISFET对，用于增强第一MISFET对的耐受电压的第二MISFET对以及具有用于锁存来自输出的第二信号的交叉耦合门的第三MISFET对。使第二MISFET对和第三MISFET对的栅极绝缘膜的膜厚比第一MISFET对的膜厚薄，并且使第一MISFET对和第二MISFET对的阈值电压小于第三MISFET对的阈值电压。即使在电平转换之前和之后的信号幅度有较大的差异，该电平转换器电路也以高速工作。

56. 发明申请

US20050237786A1 Semiconductor memories 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20050237786A1
公开(公告)日：2005-10-27
申请号：US11155780
申请日：2005-06-20
申请人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
发明人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
IPC分类号： G11C11/00 , G11C11/401 , G11C11/405 , G11C11/406 , G11C11/4076 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/12
CPC分类号： H01L27/105 , G11C11/405 , G11C11/406 , G11C11/4076 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/108 , H01L27/1203
摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
摘要翻译：本发明提供了高集成度的动态随机存取存储器。此外，提供了一种写入方法，使得减小了二晶体管和三晶体管增益单元存储器的单元尺寸。一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。通过本发明也实现了具有低操作功率和高密度的动态存储单元。

57. 发明申请

US20050218959A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20050218959A1
公开(公告)日：2005-10-06
申请号：US11048909
申请日：2005-02-03
申请人： Kentaro Yamawaki , Yoshihiko Yasu , Yasuto Igarashi , Takashi Kuraishi , Kazumasa Yanagisawa
发明人： Kentaro Yamawaki , Yoshihiko Yasu , Yasuto Igarashi , Takashi Kuraishi , Kazumasa Yanagisawa
IPC分类号： H01L21/822 , G06F1/00 , H01L23/522 , H01L27/02 , H01L27/04 , H03K17/687 , H03K19/00
CPC分类号： H01L27/0207 , H01L23/5223 , H01L24/06 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/13091 , H01L2924/14 , H01L2924/3011 , H03K17/6871 , H03K19/0016 , H01L2924/00014 , H01L2924/00
摘要： The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by: a first cell in which a first switch element for connecting a power supply voltage line or an ground voltage supply line to a power supply line of an internal circuit is disposed below a first pair of power supply lines extending in a first direction; a second cell in which a second switch element and a third switch element are disposed below a pair of second power supply lines extending in a second direction, the second switch element for connecting a first bias line connected to a first well region and a first back bias line, and the third switch element for connecting a second bias line connected to a second well region and a second back bias line; and a third cell in which a plurality of kinds of elements are spread, including a power supply switch controller for controlling the first switch element below a corner power supply line for connecting the first and pair of second power supply lines, fourth and fifth switch elements for connecting the corresponding power supply voltage line and the ground voltage supply line of the circuit to the first and second bias lines, and a control circuit for controlling switch between the fourth and fifth switch elements and the second and third switch elements.
摘要翻译：本发明提供一种提高设计效率同时实现更高功能的半导体集成电路器件。内部电路包围：第一单元，其中用于将电源电压线或地电压线连接到内部电路的电源线的第一开关元件设置在第一对延伸的电源线的下方第一个方向第二单元，其中第二开关元件和第三开关元件设置在沿第二方向延伸的一对第二电源线的下方，所述第二开关元件用于连接连接到第一阱区的第一偏置线和第一背面偏置线和用于连接连接到第二阱区和第二背偏置线的第二偏置线的第三开关元件; 以及第三单元，其中扩展了多种元件，包括用于将第一开关元件控制在用于连接第一和第二对第二电源线的角电源线下方的第一开关元件的第四开关元件和第五开关元件用于将相应的电源电压线和电路的接地电压线连接到第一和第二偏置线;以及控制电路，用于控制第四和第五开关元件与第二和第三开关元件之间的开关。

58. 发明申请

US20050146953A1 Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件
公开(公告)号：US20050146953A1
公开(公告)日：2005-07-07
申请号：US11040033
申请日：2005-01-24
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L23/528 , H01L27/092 , H03K19/00 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO 1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO 1〜MIO 4）通常用于连接电路块。

59. 发明授权

US6108264A Dynamic type semiconductor memory device 失效
标题翻译：动态型半导体存储器件
公开(公告)号：US6108264A
公开(公告)日：2000-08-22
申请号：US234101
申请日：1999-01-19
申请人： Yasushi Takahashi , Takashi Shinoda , Masamichi Ishihara , Tetsu Udagawa , Kazumasa Yanagisawa
发明人： Yasushi Takahashi , Takashi Shinoda , Masamichi Ishihara , Tetsu Udagawa , Kazumasa Yanagisawa
IPC分类号： G11C7/00 , G11C7/06 , G11C11/406
CPC分类号： G11C7/06 , G11C11/406
摘要： An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.
摘要翻译：普通的读/写操作（正常操作）和刷新操作彼此分离，并且读取的放大电路的数量，或者换句话说，使得在正常操作期间操作的读出放大器的数量小于刷新期间的读出放大器的数量操作。因此，可以减少正常工作期间的位线充电/放电电流。

60. 发明授权

US6097663A Semiconductor IC device having a memory and a logic circuit implemented with a single chip 有权
公开(公告)号：US6097663A
公开(公告)日：2000-08-01
申请号：US413641
申请日：1999-10-06
申请人： Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
发明人： Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
IPC分类号： G06F17/50 , G11C7/00 , G11C7/02 , G11C7/10 , G11C8/12 , H01L27/108 , G11C8/00
CPC分类号： G11C7/02 , G11C7/10 , G11C7/1006 , G11C7/1042 , G11C7/1072 , H01L27/10897
摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式