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51. 发明授权

US06592439B1 Platen for retaining polishing material 有权
标题翻译：压板用于保留抛光材料
公开(公告)号：US06592439B1
公开(公告)日：2003-07-15
申请号：US09709769
申请日：2000-11-10
申请人： Shijian Li , Manoocher Birang , Ramin Emami , Andrew Nagengast , Douglas Orcutt Brown , Shi-Ping Wang , Martin Scales , John White
发明人： Shijian Li , Manoocher Birang , Ramin Emami , Andrew Nagengast , Douglas Orcutt Brown , Shi-Ping Wang , Martin Scales , John White
IPC分类号： B24B2900
CPC分类号： B25B11/005 , B24B21/04 , B24B37/16 , H01L21/30625
摘要： Generally, a method and apparatus for retaining polishing material is provided. In one embodiment, the apparatus includes a platen having a top surface, a plurality of channels and one or more vacuum ports. The top surface is adapted to support the polishing material. The plurality of channels are formed in a polishing area of the top surface. The vacuum ports are disposed in the platen and at least one port is in communication with at least one of the channels. Upon application of a vacuum to the ports, the channels remove fluids under the polishing material while securing the polishing material to the top surface.
摘要翻译：通常，提供了用于保持抛光材料的方法和装置。在一个实施例中，该装置包括具有顶表面，多个通道和一个或多个真空端口的压板。顶表面适于支撑抛光材料。多个通道形成在顶表面的抛光区域中。真空端口设置在压板中，并且至少一个端口与至少一个通道连通。当向端口施加真空时，通道在将抛光材料固定到顶表面的同时移除抛光材料下面的流体。

52. 发明授权

US06585563B1 In-situ monitoring of linear substrate polishing operations 失效
标题翻译：线性衬底抛光操作的原位监控
公开(公告)号：US06585563B1
公开(公告)日：2003-07-01
申请号：US09724846
申请日：2000-11-28
申请人： Fred C. Redeker , Manoocher Birang , Shijian Li , Sasson Somekh
发明人： Fred C. Redeker , Manoocher Birang , Shijian Li , Sasson Somekh
IPC分类号： B24B100
CPC分类号： B24B37/005 , B24B21/04 , B24B49/04 , B24B49/12 , H01L21/30625
摘要： A substrate polishing scheme (apparatus and method) is described according to which a polishing surface of a polishing sheet is driven in a generally linear direction by a drive mechanism, a surface of a substrate is held against the polishing surface of the polishing sheet by a polishing head, and the substrate is probed through the polishing sheet by a monitoring system.
摘要翻译：描述了基板抛光方案（装置和方法），根据该基板抛光方案，研磨片的抛光表面通过驱动机构在大致线性方向上被驱动，基板的表面通过一个抛光头，并且通过监视系统通过抛光片探测基板。

53. 发明授权

US6162368A Technique for chemical mechanical polishing silicon 失效
标题翻译：化学机械抛光硅技术
公开(公告)号：US6162368A
公开(公告)日：2000-12-19
申请号：US97004
申请日：1998-06-13
申请人： Shijian Li , Thomas H. Osterheld , Fred C. Redeker
发明人： Shijian Li , Thomas H. Osterheld , Fred C. Redeker
IPC分类号： B24B37/04 , H01L21/304 , H01L21/306 , H01L21/321 , B44C1/22 , H01L21/00
CPC分类号： B24B37/04 , B24B37/042 , H01L21/3212
摘要： Chemical mechanical polishing of a silicon layer, such as a polycrystalline silicon, is improved by initially chemical mechanically polishing the silicon layer with an oxide-polishing slurry. Then the silicon layer is chemical mechanically polished with a silicon-polishing slurry until the substrate is planarized.
摘要翻译：通过用氧化物抛光浆料首先化学机械抛光硅层，改善硅层（例如多晶硅）的化学机械抛光。然后用硅抛光浆料对硅层进行化学机械抛光，直到基板平坦化。

54. 发明申请

US20160149935A1 DETERMINING A LEGITIMATE ACCESS POINT RESPONSE 有权
标题翻译：确定一个良好的访问点响应
公开(公告)号：US20160149935A1
公开(公告)日：2016-05-26
申请号：US14900202
申请日：2013-07-04
申请人： Yongqiang LIU , Shijian LI , Jun Qing XIE , HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： Yongqiang Liu , Shijian Li , Jun Qing Xie
IPC分类号： H04L29/06 , H04W12/10
CPC分类号： H04W12/08 , H04L47/27 , H04L47/34 , H04L63/10 , H04L63/126 , H04L63/1416 , H04W12/10 , H04W12/12 , H04W48/14 , H04W84/12
摘要： A first request is sent from a station to an access point. The station receives a first response from the access point that includes a first sequence number, and stores the first sequence number. The station sends a second request to the access point and sets a waiting period for receiving a response from the access point. The station receives a second response from the access point and a third response from a second access point during the waiting period. The second response includes a second sequence number and the third response includes a third sequence number. The station determines that the second response is a legitimate response by comparing the second and third sequence numbers to the first sequence number.
摘要翻译：第一个请求从站点发送到接入点。站从接入点接收包括第一序列号的第一响应，并存储第一序列号。该站向接入点发送第二个请求，并设置从接入点接收响应的等待时间。在等待期间，站接收来自接入点的第二响应和来自第二接入点的第三响应。第二响应包括第二序列号，第三响应包括第三序列号。通过将第二和第三序列号与第一序列号进行比较，站确定第二响应是合法响应。

55. 发明授权

US08673769B2 Methods and apparatuses for three dimensional integrated circuits 有权
标题翻译：三维集成电路的方法和装置
公开(公告)号：US08673769B2
公开(公告)日：2014-03-18
申请号：US11821051
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763
CPC分类号： H01L21/44 , H01L21/76898 , H01L23/48 , H01L23/481 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.
摘要翻译：提供了具有通孔的三维集成电路的制造方法和装置。本发明的一个方面是用于三维集成电路的通孔通孔的间隙填充方法。该方法包括提供具有用于通孔通孔的多个孔的半导体晶片，并且沉积保形金属层以部分填充孔以留下开孔。该方法还包括清除空隙并清洁空隙的表面，并使用干式沉积工艺填充或封闭空隙。本发明的另一方面是一种用于三维集成电路的电子设备结构。

56. 发明授权

US08053355B2 Methods and systems for low interfacial oxide contact between barrier and copper metallization 有权
标题翻译：屏障和铜金属化之间的低界面氧化物接触的方法和系统
公开(公告)号：US08053355B2
公开(公告)日：2011-11-08
申请号：US12828082
申请日：2010-06-30
申请人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763
CPC分类号： C25D7/123 , C23C18/1653 , C23C28/023 , C23C28/322 , C23C28/34 , C23C28/341 , H01L21/28562 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于半导体器件金属化的方法和系统。本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。该方法还包括在ALD铜上沉积间隙填充铜层。本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。在一个实施例中，集成系统包括至少一个阻挡层沉积模块。该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

57. 发明授权

US08034409B2 Methods, apparatuses, and systems for fabricating three dimensional integrated circuits 有权
标题翻译：用于制造三维集成电路的方法，装置和系统
公开(公告)号：US08034409B2
公开(公告)日：2011-10-11
申请号：US11958025
申请日：2007-12-17
申请人： Shijian Li , Fritz Redeker , Yezdi Dordi
发明人： Shijian Li , Fritz Redeker , Yezdi Dordi
IPC分类号： C23C16/00
CPC分类号： H01L21/70 , C23C16/045 , C23C16/4586 , H01L21/67017 , H01L21/677 , H01L21/6838 , H01L21/68714 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , Y10T24/44 , H01L2924/00012 , H01L2924/00
摘要： The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One embodiment of the method comprises providing a wafer or other substrate having a plurality of through holes. In addition, the method includes supporting the wafer or other substrate with a wafer or other substrate holder mounted in a process chamber. The method further includes generating a pressure differential between the front side of the wafer or other substrate and the back side of the wafer or other substrate while the wafer or other substrate is supported on the wafer or other substrate holder so that the pressure differential causes fluid flow through the through holes. Also, the method includes establishing process conditions in the process chamber for at least one process to fabricate integrated circuits. Embodiments of a system and embodiments of an apparatus according to the present invention are also presented.
摘要翻译：本发明涉及用于制造三维集成电路的方法，装置和系统。该方法的一个实施例包括提供具有多个通孔的晶片或其它基板。此外，该方法包括用安装在处理室中的晶片或其它衬底保持器来支撑晶片或其它衬底。该方法还包括在晶片或其它基板被支撑在晶片或其它基板保持器上的同时，在晶片或其它基板的前侧与晶片或其它基板的背面之间产生压差，使得压力差导致流体流过通孔。此外，该方法包括在处理室中建立用于制造集成电路的至少一个工艺的工艺条件。还提供了根据本发明的系统和实施例的装置的实施例。

58. 发明授权

US07691755B2 Plasma immersion ion implantation with highly uniform chamber seasoning process for a toroidal source reactor 有权
标题翻译：用于环形源反应器的等离子体浸没离子注入与高度均匀的室调节过程
公开(公告)号：US07691755B2
公开(公告)日：2010-04-06
申请号：US11748783
申请日：2007-05-15
申请人： Shijian Li , Lily L. Pang , Majeed A. Foad , Seon-Mee Cho
发明人： Shijian Li , Lily L. Pang , Majeed A. Foad , Seon-Mee Cho
IPC分类号： H01L21/00 , H01L21/26
CPC分类号： H01L21/2236 , H01J37/32412 , H01J37/3244 , H01J37/32449
摘要： A method is provided for performing plasma immersion ion implantation with a highly uniform seasoning film on the interior of a reactor chamber having a ceiling and a cylindrical side wall and a wafer support pedestal facing the ceiling. The method includes providing a gas distribution ring with plural gas injection orifices on a periphery of a wafer support pedestal, the orifices facing radially outwardly from the wafer support pedestal. Silicon-containing gas is introduced through the gas distribution orifices of the ring to establish a radially outward flow pattern of the silicon-containing gas. The reactor includes pairs of conduit ports in the ceiling adjacent the side wall at opposing sides thereof and respective external conduits generally spanning the diameter of the chamber and coupled to respective pairs of the ports. The method further includes injecting oxygen gas through the conduit ports into the chamber to establish an axially downward flow pattern of oxygen gas in the chamber. RF power is coupled into the interior of each of the conduits to generate a toroidal plasma current of SixOy species passing through the chamber to deposit a seasoning layer of a SixOy material on surfaces within the chamber, while leaving the pedestal without a wafer so as to expose a wafer support surface of the pedestal.
摘要翻译：提供了一种用于在具有天花板和圆柱形侧壁的反应室的内部以及面向天花板的晶片支撑台架上执行具有高度均匀的调味膜的等离子体浸没离子注入的方法。该方法包括在晶片支撑基座的外围提供具有多个气体注入孔的气体分配环，所述孔从晶片支撑基座径向向外。含硅气体通过环的气体分配孔引入，以建立含硅气体的径向向外流动图案。反应器包括在天花板中的相邻侧壁处的相对侧的导管端口对，以及相应的外部导管，其通常跨越室的直径并且耦合到相应的端口对。该方法还包括将氧气通过导管端口注入到腔室中，以在腔室中建立轴向向下的氧气气流模式。 RF功率耦合到每个导管的内部，以产生通过该室的六十种物质的环形等离子体电流，以在室内的表面上沉积SixOy材料的调味层，同时离开基座而没有晶片，以便露出基座的晶片支撑表面。

59. 发明申请

US20100062164A1 Methods and Solutions for Preventing the Formation of Metal Particulate Defect Matter Upon a Substrate After a Plating Process 审中-公开
标题翻译：电镀工艺后基体上金属微粒缺陷形成的方法与解决方案
公开(公告)号：US20100062164A1
公开(公告)日：2010-03-11
申请号：US12206509
申请日：2008-09-08
申请人： Shijian Li , Artur K. Kolics , Tiruchirapalli N. Arunagiri
发明人： Shijian Li , Artur K. Kolics , Tiruchirapalli N. Arunagiri
IPC分类号： B05D3/10 , C09K3/00 , C25D3/02
CPC分类号： C23C18/50 , C23C18/1689 , C25D5/48
摘要： Methods and solutions for preventing the formation of metal particulate defect matter upon a substrate after plating processes are provided. In particular, solutions are provided which are free of oxidizing agents and include a non-metal pH adjusting agent in sufficient concentration such that the solution has a pH between approximately 7.5 and approximately 12.0. In some cases, a solution may include a chelating agent. In addition or alternatively, a solution may include at least two different types of complexing agents each offering a single point of attachment for binding metal ions via respectively different functional groups. In any case, at least one of the complexing agents or the chelating agent includes a non-amine or non-imine functional group. An embodiment of a method for processing a substrate includes plating a metal layer upon the substrate and subsequently exposing the substrate to a solution comprising the aforementioned make-up.
摘要翻译：提供了用于防止在电镀工艺之后在基板上形成金属颗粒缺陷物质的方法和解决方案。特别地，提供了不含氧化剂的溶液，并且包括足够浓度的非金属pH调节剂，使得溶液的pH在约7.5至约12.0之间。在一些情况下，溶液可以包括螯合剂。另外或替代地，溶液可以包括至少两种不同类型的络合剂，其各自提供用于通过分别不同的官能团结合金属离子的单个附着点。在任何情况下，至少一种络合剂或螯合剂包括非胺或非亚胺官能团。用于处理衬底的方法的实施例包括将金属层电镀在衬底上，随后将衬底暴露于包含上述组成的溶液中。

60. 发明申请

US20100044867A1 METHODS OF POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION 有权
标题翻译：通过一体化的线接触后端的方法
公开(公告)号：US20100044867A1
公开(公告)日：2010-02-25
申请号：US12613518
申请日：2009-11-05
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

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