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51. 发明申请

US20060071291A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060071291A1
公开(公告)日：2006-04-06
申请号：US11236723
申请日：2005-09-28
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L31/07 , H01L21/28
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66628 , H01L29/66643 , H01L29/66795 , H01L29/78618 , H01L2029/7857
摘要： A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor comprising a semiconductor region of the first conductivity type including first and second channel regions, gate insulating films provided on the first and second channel regions, a gate electrode provided on the gate insulating films, and first and second source/drain regions which are located at a distance from each other so as to sandwich the first and second channel regions, the first and second source/drain regions contacting the semiconductor region of the first conductivity type and forming a Schottky junction.
摘要翻译：半导体器件包括半导体衬底和设置在半导体衬底上并且具有沟道类型的第一导电性的MOS晶体管，所述MOS晶体管包括第一导电类型的包括第一和第二沟道区的半导体区，提供栅极绝缘膜在第一和第二沟道区上，设置在栅极绝缘膜上的栅电极以及彼此间隔一定距离的第一和第二源极/漏极区，以夹持第一和第二沟道区，第一和第二沟道区源极/漏极区域与第一导电类型的半导体区域接触并形成肖特基结。

52. 发明申请

US20050167766A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050167766A1
公开(公告)日：2005-08-04
申请号：US10874211
申请日：2004-06-24
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/786 , H01L29/76
CPC分类号： H01L21/823443 , H01L21/28194 , H01L21/823418 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4975 , H01L29/517 , H01L29/7839
摘要： A semiconductor device includes a semiconductor substrate containing silicon, a p-type semiconductor active region formed on the semiconductor substrate, a first gate insulating film containing at least one of Zr and Hf and formed on the p-type semiconductor active region, a first gate electrode formed on the first gate insulating film and formed of first silicide containing silicon and a first metal material and having a work function level lower than the central position of a band gap of the p-type semiconductor active region, and a first source region and first drain region configured by a second silicide containing silicon and the first metal material and formed to sandwich the p-type semiconductor active region.
摘要翻译：半导体器件包括含硅的半导体衬底，形成在半导体衬底上的p型半导体有源区，包含至少一个Zr和Hf并形成在p型半导体有源区上的第一栅极绝缘膜，第一栅极电极，形成在第一栅极绝缘膜上，并且由含有硅和第一金属材料的第一硅化物形成，并且具有低于p型半导体有源区的带隙的中心位置的功函数级，以及第一源极区和第一漏极区域由包含硅的第二硅化物和第一金属材料构成并形成为夹持p型半导体有源区。

53. 发明授权

US06887747B2 Method of forming a MISFET having a schottky junctioned silicide 有权
标题翻译：形成具有肖特基结的硅化物的MISFET的方法
公开(公告)号：US06887747B2
公开(公告)日：2005-05-03
申请号：US10205203
申请日：2002-07-26
申请人： Atsushi Yagishita , Kouji Matsuo
发明人： Atsushi Yagishita , Kouji Matsuo
IPC分类号： H01L21/283 , H01L21/28 , H01L21/335 , H01L21/336 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L27/095 , H01L29/417 , H01L29/45 , H01L29/47 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/786 , H01L29/872 , H01L21/8234
CPC分类号： H01L21/28194 , H01L21/823814 , H01L21/823828 , H01L27/095 , H01L29/41733 , H01L29/458 , H01L29/47 , H01L29/4908 , H01L29/51 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66583 , H01L29/66643 , H01L29/7839
摘要： There is disclosed a semiconductor device in which a device isolating insulating film is formed in a periphery of a device region of a semiconductor silicon substrate device region. A side wall insulating film formed of a silicon nitride film is formed to cover the periphery of a channel region on the silicon substrate. A Ta2O5 film, and a metal gate electrode are formed inside a trench whose side wall is formed of the side wall insulating film. An interlayer insulating film is formed on the device isolating insulating film. A Schottky source/drain formed of silicide is formed on the silicon substrate in a bottom portion of the trench whose side wall is formed of the side wall insulating film and interlayer insulating film. A source/drain electrode is formed on the Schottky source/drain.
摘要翻译：公开了一种半导体器件，其中在半导体硅衬底器件区域的器件区域的周围形成器件隔离绝缘膜。形成由氮化硅膜形成的侧壁绝缘膜，以覆盖硅衬底上的沟道区的周边。在其侧壁由侧壁绝缘膜形成的沟槽内部形成有一个Ta 2 O 5 O 5膜和金属栅电极。在器件隔离绝缘膜上形成层间绝缘膜。在沟槽的底部的硅衬底上形成由硅化物形成的肖特基源极/漏极，其侧壁由侧壁绝缘膜和层间绝缘膜形成。源极/漏电极形成在肖特基源/漏极上。

54. 发明申请

US20110147839A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147839A1
公开(公告)日：2011-06-23
申请号：US12640658
申请日：2009-12-17
申请人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
发明人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.
摘要翻译：提供多栅极金属氧化物硅晶体管和制造多栅极金属氧化物硅晶体管的方法。多栅极金属氧化物硅晶体管包含在浅沟槽区域之间包含一个或多个凸部的体硅衬底; 一个或多个在凸部上的电介质部分; 电介质部分上的一个或多个硅散热片; 在浅沟槽隔离区域的浅沟槽隔离层; 和栅电极。浅沟槽隔离层的上表面可以位于凸部的上表面下方，或者浅沟槽隔离层的上表面可以位于第一介电层的下表面和上表面之间。多栅极金属氧化物硅晶体管可以包含与源极/漏极区域中的凸部的侧表面相邻的第二间隔物。

55. 发明授权

US07820551B2 Semiconductor device having fins FET and manufacturing method thereof 有权
标题翻译：具有翅片FET的半导体器件及其制造方法
公开(公告)号：US07820551B2
公开(公告)日：2010-10-26
申请号：US11972097
申请日：2008-01-10
申请人： Atsushi Yagishita , Akio Kaneko
发明人： Atsushi Yagishita , Akio Kaneko
IPC分类号： H01L21/311
CPC分类号： H01L29/785 , H01L29/0673 , H01L29/42392 , H01L29/66795 , H01L29/7854 , H01L29/78639
摘要： A line-form insulator is formed on a substrate and then the substrate is etched with the insulator used as a mask to form first trenches on both sides of the insulator. Side wall insulators are formed on the side walls of the first trenches, the substrate is etched with the insulator and side wall insulators used as a mask to form second trenches in the bottom of the first trenches. After, the substrate is oxidized with the insulator and side wall insulators used as an anti-oxidation mask to cause oxide regions formed on the adjacent side walls of the second trenches lying on both sides of the substrate to make contact with each other and the insulator and side wall insulators are removed. Then, a fin FET having a semiconductor region as a line-form fin is formed in the substrate.
摘要翻译：在衬底上形成线形绝缘体，然后用用作掩模的绝缘体蚀刻衬底，以在绝缘体的两侧形成第一沟槽。侧壁绝缘体形成在第一沟槽的侧壁上，用绝缘体和侧壁绝缘体作为掩模蚀刻衬底，以在第一沟槽的底部形成第二沟槽。之后，用作为抗氧化掩模的绝缘体和侧壁绝缘体氧化衬底，使得形成在位于衬底两侧的第二沟槽的相邻侧壁上形成的氧化物区域相互接触，并且绝缘体和侧壁绝缘子被去除。然后，在衬底中形成具有半导体区域作为线状翅片的翅片FET。

56. 发明授权

US07755104B2 FinFET pMOS double gate semiconductor device with uniaxial tensile strain applied to channel by shrinkable gate electrode material, current flow in <110> crystal orientation, and source and drain Schottky contacts with channel and manufacturing method thereof 有权
标题翻译： FinFET pMOS双栅极半导体器件具有通过可收缩的栅电极材料施加到沟道的单轴拉伸应变，<110>晶体取向的电流流动，以及沟道的源极和漏极肖特基接触及其制造方法
公开(公告)号：US07755104B2
公开(公告)日：2010-07-13
申请号：US11790389
申请日：2007-04-25
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L29/04 , H01L21/84
CPC分类号： H01L29/045 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/7842 , H01L29/7845 , H01L29/785 , H01L29/78684
摘要： A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second crystal orientation perpendicular to the current flow direction, and a gate insulating film that is disposed between the semiconductor layer and the gate electrode, wherein a uniaxial tensile strain is applied to the semiconductor layer in the direction of the second crystal orientation perpendicular to the current flow direction.
摘要翻译：具有pMOS双栅极结构的半导体器件具有衬底，其表面的晶体取向为（100），由硅或锗制成的半导体层，形成在衬底上，使得电流流过第一<110>晶体取向的方向，并且沟道位于半导体层的侧壁处，源极层在与第一<110>晶体取向的方向相邻的半导体层的一端形成在基板上，以及由金属或金属硅化物形成与半导体层的肖特基结; 漏极层，其形成在与第一<110>晶体取向方向相邻的半导体层的另一端的基板上，并且由金属或金属硅化物形成，以与半导体层形成肖特基结; 在垂直于电流流动方向的第二<110>晶体取向的方向上形成在半导体层上的栅电极，以及设置在半导体层和栅电极之间的栅极绝缘膜，其中单轴拉伸应变沿垂直于电流流动方向的第二<110>晶体取向的方向施加到半导体层。

57. 发明申请

US20090174036A1 PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES 审中-公开
标题翻译：等离子体固化材料的等离子体刻蚀特性
公开(公告)号：US20090174036A1
公开(公告)日：2009-07-09
申请号：US11969525
申请日：2008-01-04
申请人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
发明人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
IPC分类号： H01L29/30 , G03F7/26
CPC分类号： G03F7/40
摘要： A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing.
摘要翻译：公开了一种能够在光刻图案化之后显着降低线边缘粗糙度（LER）和线宽粗糙度（LEW）来制造半导体器件（即STI结构，栅极和互连）的方法。本发明的方法需要使用含有等离子体的惰性物质来调整光刻后的真空紫外（VUV）发射和/或给定特征（在相同的蚀刻平台上）的一个蚀刻工艺，以引发增加的交联的一个或多个图案形成材料，因此能够提高耐蚀刻性和减少LER和LEW后蚀刻处理。

58. 发明授权

US07462917B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07462917B2
公开(公告)日：2008-12-09
申请号：US11411909
申请日：2006-04-27
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L27/088
CPC分类号： H01L29/7851 , H01L29/66795
摘要： According to the present invention, there is provided a semiconductor device having:first and second fins formed on a semiconductor substrate to oppose each other, and made of a semiconductor layer;an active region which is formed on the semiconductor substrate so as to be connected to the first and second fins, and supplies a predetermined voltage to the first and second fins; anda gate electrode formed on an insulating film formed on the semiconductor substrate, in a position separated from the active region by a predetermined spacing, so as to cross the first and second fins,wherein in the active region, a predetermined portion between a first portion connected to the first fin and a second portion connected to the second fin is removed.
摘要翻译：根据本发明，提供了一种半导体器件，其具有：形成在半导体衬底上的第一和第二鳍片彼此相对，并由半导体层制成; 形成在所述半导体基板上以与第一和第二散热片连接并将预定电压提供给第一和第二散热片的有源区; 以及栅电极，形成在形成在所述半导体基板上的绝缘膜上，在与所述有源区隔开预定间隔的位置处，以跨越所述第一和第二鳍片，其中在所述有源区域中，在第一连接到第一翅片的部分和连接到第二翅片的第二部分被去除。

59. 发明申请

US20080220582A1 Semiconductor device and method of fabricating the same 失效
公开(公告)号：US20080220582A1
公开(公告)日：2008-09-11
申请号：US12078585
申请日：2008-04-02
申请人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
发明人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region; depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; and patterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.

60. 发明申请

US20070235819A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070235819A1
公开(公告)日：2007-10-11
申请号：US11717067
申请日：2007-03-13
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/785 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/78621 , H01L29/78684
摘要： There is provided a semiconductor device including: convex semiconductor layers formed on a semiconductor substrate via an insulating film; gate electrodes formed on a pair of facing sides of the semiconductor layers via a gate insulating film; a channel region formed of silicon between the gate electrodes in the semiconductor layers; a source extension region and a drain extension region formed of silicon germanium or silicon carbon on both sides of the channel region in the semiconductor layers; and a source region formed of silicon so as to adjoin to the opposite side of the channel region in the source extension region, and a drain region formed of silicon so as to adjoin to the opposite side of the channel region in the drain extension region in the semiconductor layers.
摘要翻译：提供了一种半导体器件，包括：通过绝缘膜形成在半导体衬底上的凸形半导体层; 经由栅极绝缘膜形成在半导体层的一对相对侧上的栅电极; 在半导体层中的栅电极之间由硅形成的沟道区; 源极延伸区域和在半导体层中的沟道区域的两侧上由硅锗或硅碳形成的漏极延伸区域; 以及由硅形成的源极区域，以与源极延伸区域中的沟道区域的相对侧相邻，以及由硅形成的漏极区域，以与漏极延伸区域中的沟道区域的相对侧邻接半导体层。

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