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51. 发明申请

US20070099405A1 Methods for fabricating multi-terminal phase change devices 有权
标题翻译：制造多端相变装置的方法
公开(公告)号：US20070099405A1
公开(公告)日：2007-05-03
申请号：US11267789
申请日：2005-11-03
申请人： Antonietta Oliva , Louis Kordus , Narbeh Derhacobian , Vei-Han Chan , Thomas Stewart
发明人： Antonietta Oliva , Louis Kordus , Narbeh Derhacobian , Vei-Han Chan , Thomas Stewart
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/126
摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
摘要翻译：相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其导电性可以根据施加到控制电极的控制信号进行修改。这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。加热元件的电阻不影响相变装置的总电阻。编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

52. 发明授权

US06962848B2 Nonvolatile memory structures and fabrication methods 有权
标题翻译：非易失性存储器结构和制造方法
公开(公告)号：US06962848B2
公开(公告)日：2005-11-08
申请号：US10689908
申请日：2003-10-20
申请人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
发明人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.
摘要翻译：为了制造半导体存储器，在半导体衬底上形成一对或多对第一结构。每个第一结构包括（a）存储器单元的多个浮动栅极和（b）为存储器单元提供控制栅极的第一导电线。控制门覆盖浮动门。每对第一结构对应于多个掺杂区域，每个掺杂区域向存储单元提供源极/漏极区域，该存储器单元具有在一个或者结构中的浮动栅极和控制栅极，并且源极/漏极区域到具有浮置和/ 在另一个结构中控制门。对于每对，形成第二导线，其底表面在两个结构之间延伸并物理地接触对应的第一掺杂区域。在一些实施例中，第一掺杂区域被绝缘沟槽分开。第二导线可以形成至少部分地填充两个第一结构之间的区域的导电插塞。

53. 发明申请

US20050227437A1 Method of forming ONO-type sidewall with reduced bird's beak 有权
标题翻译：用鸟喙形成ONO型侧壁的方法
公开(公告)号：US20050227437A1
公开(公告)日：2005-10-13
申请号：US10821100
申请日：2004-04-07
申请人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Leung , Chia-Shun Hsiao , George Kovall , Steven Yang
发明人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Leung , Chia-Shun Hsiao , George Kovall , Steven Yang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/788
CPC分类号： H01L21/28273 , H01L29/42328 , H01L29/513 , H01L29/7881
摘要： Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.
摘要翻译：通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分材料堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。结果，氧化不沿着侧壁的多层高度均匀地进行。本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为深深地通过侧壁的已氧化层，例如氧化硅层。结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

54. 发明授权

US06584018B2 Nonvolatile memory structures and access methods 有权
公开(公告)号：US06584018B2
公开(公告)日：2003-06-24
申请号：US09972388
申请日：2001-10-05
申请人： Hsing T. Tuan , Li-Chun Li , Vei-Han Chan
发明人： Hsing T. Tuan , Li-Chun Li , Vei-Han Chan
IPC分类号： G11C1134
CPC分类号： G11C16/08 , G11C8/08
摘要： In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

55. 发明授权

US06562681B2 Nonvolatile memories with floating gate spacers, and methods of fabrication 有权
公开(公告)号：US06562681B2
公开(公告)日：2003-05-13
申请号：US09881288
申请日：2001-06-13
申请人： Hsing T. Tuan , Vei-Han Chan , Chung-Wai Leung , Chia-Shun Hsiao
发明人： Hsing T. Tuan , Vei-Han Chan , Chung-Wai Leung , Chia-Shun Hsiao
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/42336
摘要： In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

56. 发明授权

US06262622B1 Breakdown-free high voltage input circuitry 失效
标题翻译：无击穿高压输入电路
公开(公告)号：US06262622B1
公开(公告)日：2001-07-17
申请号：US09479649
申请日：2000-01-08
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen
IPC分类号： G05F302
CPC分类号： G05F3/242
摘要： A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.
摘要翻译：高压输入电路包括三阱NMOS，用于减小跨越其漏极结的电压应力，以防止其击穿。三阱NMOS在P衬底中形成在深N阱中的P阱中制造。 P阱通过P阱电压控制装置耦合到电源电压，以减少跨越漏极结的电压差。低电压信号输入电路部分也被添加到高电压输入电路，以允许高电压输入引脚接收其它信号并减少集成电路的总引脚数。在低电压信号输入电路中使用诸如NAND门而不是反相器的双输入缓冲器，用于降低对低电压信号输入电路中的器件的电压应力。

57. 发明授权

US06252276B1 Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide 有权
标题翻译：非易失性半导体存储器件包括非均匀氮掺杂的栅极氧化物
公开(公告)号：US06252276B1
公开(公告)日：2001-06-26
申请号：US09377183
申请日：1999-08-19
申请人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
发明人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
IPC分类号： H01L2978
CPC分类号： H01L21/28202 , H01L21/28273 , H01L29/518 , H01L29/66825
摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.
摘要翻译：提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

58. 发明授权

US6134150A Erase condition for flash memory 有权
标题翻译：擦除闪存的条件
公开(公告)号：US6134150A
公开(公告)日：2000-10-17
申请号：US360315
申请日：1999-07-23
申请人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Vei-Han Chan , Hung-Sheng Chen
发明人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Vei-Han Chan , Hung-Sheng Chen
IPC分类号： G11C16/14 , G11C7/00
CPC分类号： G11C16/14
摘要： In the present invention a flash memory configuration is disclosed that eliminates the need for one of two pump circuits that are commonly required to support an erase function of memory cells on a flash memory chip. The flash memory cells are placed into a triple well structure with a P-well contained within a deep N-well that resides on a P-substrate. The bias voltages for erase of the flash memory cells are chosen so as to require only one voltage pump circuit to be included in the flash memory chip. The chip bias, V.sub.DD, is used for the source of the memory cells and a negative gate voltage is raised in magnitude to maintain the efficiency of the erase operation. The P-well is biased with a negative voltage that is sufficient to prevent the high negative voltage connected to the gate from causing breakdown in word line decoder circuits. The deep N-well and the P-substrate are biased such as to back bias the P/N junctions between the triple well structure.
摘要翻译：在本发明中，公开了一种闪存配置，其不需要通常需要两个泵电路之一来支持闪存芯片上的存储器单元的擦除功能。将闪存单元置于三阱结构中，其中P阱包含在驻留在P基底上的深N阱内。选择用于擦除闪存单元的偏置电压，以便仅需要将一个电压泵电路包括在闪存芯片中。芯片偏置VDD用于存储单元的源极，负栅极电压上升幅度以保持擦除操作的效率。 P阱被施加负电压，该负电压足以防止连接到栅极的高负电压引起字线解码器电路中的击穿。深N阱和P衬底被偏置，以便反向偏置三阱结构之间的P / N结。

59. 发明授权

US5972751A Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device 有权
标题翻译：在非易失性半导体存储器件中将氮引入隧道氧化物的方法和装置
公开(公告)号：US5972751A
公开(公告)日：1999-10-26
申请号：US143090
申请日：1998-08-28
申请人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
发明人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51
CPC分类号： H01L21/28202 , H01L21/28273 , H01L29/518 , H01L29/66825
摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.
摘要翻译：提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

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