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1. 发明授权

US06660585B1 Stacked gate flash memory cell with reduced disturb conditions 有权
标题翻译：具有减少干扰条件的堆叠式门闪存单元
公开(公告)号：US06660585B1
公开(公告)日：2003-12-09
申请号：US09531787
申请日：2000-03-21
申请人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , G11C16/0416 , H01L21/28273
摘要： In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.
摘要翻译：在本发明中，公开了一种堆叠栅极闪存单元，其在器件的漏极侧具有轻掺杂漏极（LDD），并且使用源使用热电子发生进行编程并使用Fowler-Nordheim隧道擦除浮动栅极。通过利用LDD和使用源进行编程和擦除的单元的偏置来减少干扰条件。作为减少热电子产生的LDD的结果，漏极的电场大大减小。 LDD还有助于在编程期间减少位线干扰条件。通过将未选择的单元的位线预处理为Vcc，使未选择的单元中的瞬态位线干扰条件最小化。

2. 发明授权

US6134150A Erase condition for flash memory 有权
标题翻译：擦除闪存的条件
公开(公告)号：US6134150A
公开(公告)日：2000-10-17
申请号：US360315
申请日：1999-07-23
申请人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Vei-Han Chan , Hung-Sheng Chen
发明人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Vei-Han Chan , Hung-Sheng Chen
IPC分类号： G11C16/14 , G11C7/00
CPC分类号： G11C16/14
摘要： In the present invention a flash memory configuration is disclosed that eliminates the need for one of two pump circuits that are commonly required to support an erase function of memory cells on a flash memory chip. The flash memory cells are placed into a triple well structure with a P-well contained within a deep N-well that resides on a P-substrate. The bias voltages for erase of the flash memory cells are chosen so as to require only one voltage pump circuit to be included in the flash memory chip. The chip bias, V.sub.DD, is used for the source of the memory cells and a negative gate voltage is raised in magnitude to maintain the efficiency of the erase operation. The P-well is biased with a negative voltage that is sufficient to prevent the high negative voltage connected to the gate from causing breakdown in word line decoder circuits. The deep N-well and the P-substrate are biased such as to back bias the P/N junctions between the triple well structure.
摘要翻译：在本发明中，公开了一种闪存配置，其不需要通常需要两个泵电路之一来支持闪存芯片上的存储器单元的擦除功能。将闪存单元置于三阱结构中，其中P阱包含在驻留在P基底上的深N阱内。选择用于擦除闪存单元的偏置电压，以便仅需要将一个电压泵电路包括在闪存芯片中。芯片偏置VDD用于存储单元的源极，负栅极电压上升幅度以保持擦除操作的效率。 P阱被施加负电压，该负电压足以防止连接到栅极的高负电压引起字线解码器电路中的击穿。深N阱和P衬底被偏置，以便反向偏置三阱结构之间的P / N结。

3. 发明授权

US06262622B1 Breakdown-free high voltage input circuitry 失效
标题翻译：无击穿高压输入电路
公开(公告)号：US06262622B1
公开(公告)日：2001-07-17
申请号：US09479649
申请日：2000-01-08
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen
IPC分类号： G05F302
CPC分类号： G05F3/242
摘要： A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.
摘要翻译：高压输入电路包括三阱NMOS，用于减小跨越其漏极结的电压应力，以防止其击穿。三阱NMOS在P衬底中形成在深N阱中的P阱中制造。 P阱通过P阱电压控制装置耦合到电源电压，以减少跨越漏极结的电压差。低电压信号输入电路部分也被添加到高电压输入电路，以允许高电压输入引脚接收其它信号并减少集成电路的总引脚数。在低电压信号输入电路中使用诸如NAND门而不是反相器的双输入缓冲器，用于降低对低电压信号输入电路中的器件的电压应力。

4. 发明授权

US07372736B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07372736B2
公开(公告)日：2008-05-13
申请号：US11391662
申请日：2006-03-28
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , H01L29/76 , H01L23/544
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

5. 发明授权

US07120064B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US07120064B2
公开(公告)日：2006-10-10
申请号：US11036961
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

6. 发明授权

US07102929B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07102929B2
公开(公告)日：2006-09-05
申请号：US11036835
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

7. 发明授权

US07064978B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07064978B2
公开(公告)日：2006-06-20
申请号：US10351180
申请日：2003-01-24
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , H01L29/76 , H01L23/544
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

8. 发明授权

US6009022A Node-precise voltage regulation for a MOS memory system 有权
标题翻译：用于MOS存储器系统的节点精确电压调节
公开(公告)号：US6009022A
公开(公告)日：1999-12-28
申请号：US189109
申请日：1998-11-09
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C16/30 , G11C7/00
CPC分类号： G11C7/12 , G11C16/30 , G11C5/147 , G11C8/08
摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.
摘要翻译：片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压。位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较差分输出比较器。用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。

9. 发明授权

US5835420A Node-precise voltage regulation for a MOS memory system 失效
标题翻译：用于MOS存储器系统的节点精确电压调节
公开(公告)号：US5835420A
公开(公告)日：1998-11-10
申请号：US884251
申请日：1997-06-27
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C16/30 , G11C7/00
CPC分类号： G11C7/12 , G11C16/30 , G11C5/147 , G11C8/08
摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from at least one of which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.
摘要翻译：片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压中的至少一个。位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较差分输出比较器。用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。

10. 发明授权

US5682350A Flash memory with divided bitline 失效
标题翻译：闪存分频线
公开(公告)号：US5682350A
公开(公告)日：1997-10-28
申请号：US726670
申请日：1996-10-07
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3409 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/08 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A flash memory includes a bank of flash transistors forming a plurality of rows and a plurality of columns, each flash transistor having a gate, drain and source, where the gates of flash transistors in each row are coupled to common wordlines, the drains of flash transistors in each column are coupled to common metal 1 lines divided into even metal 1 lines and odd metal 1 lines and the sources of the flash transistors are coupled to a common sourceline. A set of first selection transistors are coupled between even metal 1 lines and metal 2 lines having a pitch twice that of said metal 1 lines and controlled by a first select signal to selectively couple the even metal 1 lines to the metal 2 lines. A set of second selection transistors are coupled between odd metal 1 lines and the metal 2 lines and controlled by a second select signal to selectively couple the odd metal 1 lines to the metal 2 lines. In one embodiment, the set of first selection transistors and the set of second selection transistors are large in comparison to the flash transistors. Advantages of the invention include improved selection of memory cells, higher memory cell density and lower resistance in the memory cell selection circuitry.
摘要翻译：闪速存储器包括形成多行和多列的闪存晶体管组，每个闪存晶体管具有栅极，漏极和源极，其中每行中的闪存晶体管的栅极耦合到公共字线，闪存的漏极每列中的晶体管耦合到分为偶数金属1线和奇数金属1线的公共金属1线，并且闪存晶体管的源耦合到公共源极线。一组第一选择晶体管耦合在偶数金属1线和金属2线之间，金属2线具有两倍于所述金属1线的间距，并由第一选择信号控制，以选择性地将偶数金属1线耦合到金属2线。一组第二选择晶体管耦合在奇数金属1线和金属2线之间，并由第二选择信号控制，以将奇数金属1线选择性地耦合到金属2线。在一个实施例中，与闪存晶体管相比，该组第一选择晶体管和该组第二选择晶体管较大。本发明的优点包括存储器单元的改进选择，更高的存储单元密度和较低的存储单元选择电路中的电阻。

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