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1. 发明授权

US07910429B2 Method of forming ONO-type sidewall with reduced bird's beak 有权
标题翻译：用鸟喙形成ONO型侧壁的方法
公开(公告)号：US07910429B2
公开(公告)日：2011-03-22
申请号：US10821100
申请日：2004-04-07
申请人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao , George Kovall , Steven Ming Yang
发明人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao , George Kovall , Steven Ming Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/42328 , H01L29/513 , H01L29/7881
摘要： Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.
摘要翻译：通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分材料堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。结果，氧化不沿着侧壁的多层高度均匀地进行。本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为深深地通过侧壁的已氧化层，例如氧化硅层。结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

2. 发明授权

US06821847B2 Nonvolatile memory structures and fabrication methods 有权
公开(公告)号：US06821847B2
公开(公告)日：2004-11-23
申请号：US09969841
申请日：2001-10-02
申请人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
发明人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

3. 发明授权

US06815760B2 Nonvolatile memory structures and fabrication methods 有权
公开(公告)号：US06815760B2
公开(公告)日：2004-11-09
申请号：US10200443
申请日：2002-07-22
申请人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
发明人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

4. 发明授权

US06570215B2 Nonvolatile memories with floating gate spacers, and methods of fabrication 有权
公开(公告)号：US06570215B2
公开(公告)日：2003-05-27
申请号：US10199157
申请日：2002-07-18
申请人： Hsing T. Tuan , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao
发明人： Hsing T. Tuan , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao
IPC分类号： H01L2362
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/42336
摘要： In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

5. 发明授权

US06962848B2 Nonvolatile memory structures and fabrication methods 有权
标题翻译：非易失性存储器结构和制造方法
公开(公告)号：US06962848B2
公开(公告)日：2005-11-08
申请号：US10689908
申请日：2003-10-20
申请人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
发明人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.
摘要翻译：为了制造半导体存储器，在半导体衬底上形成一对或多对第一结构。每个第一结构包括（a）存储器单元的多个浮动栅极和（b）为存储器单元提供控制栅极的第一导电线。控制门覆盖浮动门。每对第一结构对应于多个掺杂区域，每个掺杂区域向存储单元提供源极/漏极区域，该存储器单元具有在一个或者结构中的浮动栅极和控制栅极，并且源极/漏极区域到具有浮置和/ 在另一个结构中控制门。对于每对，形成第二导线，其底表面在两个结构之间延伸并物理地接触对应的第一掺杂区域。在一些实施例中，第一掺杂区域被绝缘沟槽分开。第二导线可以形成至少部分地填充两个第一结构之间的区域的导电插塞。

6. 发明授权

US06562681B2 Nonvolatile memories with floating gate spacers, and methods of fabrication 有权
公开(公告)号：US06562681B2
公开(公告)日：2003-05-13
申请号：US09881288
申请日：2001-06-13
申请人： Hsing T. Tuan , Vei-Han Chan , Chung-Wai Leung , Chia-Shun Hsiao
发明人： Hsing T. Tuan , Vei-Han Chan , Chung-Wai Leung , Chia-Shun Hsiao
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/42336
摘要： In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

7. 发明申请

US20050227437A1 Method of forming ONO-type sidewall with reduced bird's beak 有权
标题翻译：用鸟喙形成ONO型侧壁的方法
公开(公告)号：US20050227437A1
公开(公告)日：2005-10-13
申请号：US10821100
申请日：2004-04-07
申请人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Leung , Chia-Shun Hsiao , George Kovall , Steven Yang
发明人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Leung , Chia-Shun Hsiao , George Kovall , Steven Yang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/788
CPC分类号： H01L21/28273 , H01L29/42328 , H01L29/513 , H01L29/7881
摘要： Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.
摘要翻译：通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分材料堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。结果，氧化不沿着侧壁的多层高度均匀地进行。本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为深深地通过侧壁的已氧化层，例如氧化硅层。结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

8. 发明授权

US07696018B2 Methods for fabricating multi-terminal phase change devices 有权
标题翻译：制造多端相变装置的方法
公开(公告)号：US07696018B2
公开(公告)日：2010-04-13
申请号：US12116911
申请日：2008-05-07
申请人： Antonietta Oliva , Louis Charles Kordus, II , Narbeh Derharcobian , Vei-Han Chan , Thomas E. Stewart, Jr.
发明人： Antonietta Oliva , Louis Charles Kordus, II , Narbeh Derharcobian , Vei-Han Chan , Thomas E. Stewart, Jr.
IPC分类号： H01L21/06 , H01L45/00
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/126
摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
摘要翻译：相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，该相变材料的导电性可以根据施加到控制电极的控制信号进行修改。这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。加热元件的电阻不影响相变装置的总电阻。编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

9. 发明授权

US06674669B2 Nonvolatile memory structures and access methods 有权
标题翻译：非易失性存储器结构和访问方法
公开(公告)号：US06674669B2
公开(公告)日：2004-01-06
申请号：US10268863
申请日：2002-10-09
申请人： Hsing T. Tuan , Li-Chun Li , Vei-Han Chan
发明人： Hsing T. Tuan , Li-Chun Li , Vei-Han Chan
IPC分类号： G11C1134
CPC分类号： G11C16/08 , G11C8/08
摘要： In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.
摘要翻译：在非易失性存储器阵列的每行中，所有存储器单元的选择栅极连接在一起，并用于选择用于存储器存取的行。每行的控制栅极也连接在一起，并且每行的源极区域连接在一起。此外，多行的控制栅极连接在一起，并且多行的源极区域连接在一起，但是如果两行的源极区域连接在一起，则它们的控制栅极不连接在一起。如果两行中的一个被访问，但是两行中的另一行未被访问，则它们的控制栅极被驱动到不同的电压，从而降低在未访问行中穿透的可能性。

10. 发明授权

US06660585B1 Stacked gate flash memory cell with reduced disturb conditions 有权
标题翻译：具有减少干扰条件的堆叠式门闪存单元
公开(公告)号：US06660585B1
公开(公告)日：2003-12-09
申请号：US09531787
申请日：2000-03-21
申请人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , G11C16/0416 , H01L21/28273
摘要： In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.
摘要翻译：在本发明中，公开了一种堆叠栅极闪存单元，其在器件的漏极侧具有轻掺杂漏极（LDD），并且使用源使用热电子发生进行编程并使用Fowler-Nordheim隧道擦除浮动栅极。通过利用LDD和使用源进行编程和擦除的单元的偏置来减少干扰条件。作为减少热电子产生的LDD的结果，漏极的电场大大减小。 LDD还有助于在编程期间减少位线干扰条件。通过将未选择的单元的位线预处理为Vcc，使未选择的单元中的瞬态位线干扰条件最小化。

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