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    • 56. 发明授权
    • Method of fabricating semiconductor device
    • 制造半导体器件的方法
    • US06617240B2
    • 2003-09-09
    • US09748230
    • 2000-12-27
    • Yasunori InoueNaoteru MatsubaraHidetaka NishimuraHideki Mizuhara
    • Yasunori InoueNaoteru MatsubaraHidetaka NishimuraHideki Mizuhara
    • H01L214763
    • H01L21/76877H01L21/76802H01L21/76825H01L21/76828
    • A method of fabricating a semiconductor device capable of attaining an excellent embedding characteristic also when an opening has a small diameter is obtained. According to this method of fabricating a semiconductor device, an interlayer dielectric film having an opening is formed. A first conductive member is formed in the opening by sputtering. In advance of formation of the first conductive member, first heat treatment is performed at a temperature capable of reducing the quantity of moisture and hydroxyl groups in the interlayer dielectric film. Thus, the interlayer dielectric film has a small quantity of moisture and hydroxyl groups when the first conductive member is embedded in the opening, whereby the embedding characteristic of the first conductive member is improved. Consequently, electric characteristics of a contact part can be improved also when the opening has a small diameter.
    • 获得了当开口具有小直径时也能够获得优异的嵌入特性的半导体器件的制造方法。 根据制造半导体器件的这种方法,形成具有开口的层间绝缘膜。 通过溅射在开口中形成第一导电构件。 在形成第一导电部件之前,首先在能够降低层间电介质膜的湿度和羟基量的温度下进行热处理。 因此,当第一导电部件嵌入开口时,层间电介质膜具有少量的水分和羟基,从而提高了第一导电部件的嵌入特性。 因此,当开口具有小直径时,也可以提高接触部的电特性。
    • 57. 发明授权
    • Method of making a dual damascene structure with modified insulation
    • 制造具有改性绝缘材料的双镶嵌结构的方法
    • US06399478B2
    • 2002-06-04
    • US09788661
    • 2001-02-21
    • Naoteru MatsubaraHideki Mizuhara
    • Naoteru MatsubaraHideki Mizuhara
    • H01L214763
    • H01L21/76825H01L21/76807
    • A semiconductor device having a dual damascene structure having a highly reliable multilayered interconnection is applied to the present invention. A protective film (12) is formed on a first interconnection (11), and a modified SOG film (13a) is then provided thereon. An etch stopper film (14) is formed on the modified SOG film (13a), and a modified SOG film (15a) is then formed. The modified SOG film (15a), the etch stopper film (14), and the modified SOG film (13a) are etched away using a resist pattern, to form a via hole (17). The modified SOG film (15a) is etched away using the resist pattern, to form a recess (19) serving as a trench interconnection portion. The etch stopper film (14) and the protective film (12) which are exposed are removed, and the recess is filled with a conductive material (20), to form a conductive plug in the via hole and a second interconnection.
    • 具有高度可靠的多层互连的双镶嵌结构的半导体器件被应用于本发明。 在第一互连(11)上形成保护膜(12),然后在其上提供改性SOG膜(13a)。 在改性SOG膜(13a)上形成蚀刻停止膜(14),然后形成改性SOG膜(15a)。 使用抗蚀剂图案蚀刻掉改性SOG膜(15a),蚀刻停止膜(14)和改性SOG膜(13a),以形成通孔(17)。 使用抗蚀剂图案蚀刻掉改性SOG膜(15a),形成用作沟槽互连部分的凹部(19)。 去除暴露的蚀刻停止膜(14)和保护膜(12),并且用导电材料(20)填充凹部,以在通孔和第二互连中形成导电塞。