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    • 55. 发明申请
    • Memory Access Apparatus
    • 存储器访问装置
    • US20070242533A1
    • 2007-10-18
    • US11734749
    • 2007-04-12
    • Kazuhiro NakamutaIwao HondaTakashi Kuroda
    • Kazuhiro NakamutaIwao HondaTakashi Kuroda
    • G11C7/10
    • G11C7/1039G11C7/1051G11C7/106G11C7/1066G11C7/22G11C8/06
    • A memory access apparatus reading data from a memory, the memory including a terminal that address information is input to, a terminal that a clock signal changing at a predetermined cycle is input to, a terminal that a read command is input to, and a terminal that outputs data stored at an address identified by the address information at a timing of the clock signal changing from one level to the other level in accordance with the read command, the memory access apparatus comprising: an address information output unit that outputs the address information and the read command at a first timing of the clock signal changing from the one level to the other level; and a read data storage unit that stores data output from the memory at a second timing after the first timing of the clock signal changing from the one level to the other level, the read data storage unit storing the data at a third timing after the second timing of the clock signal changing from the one level to the other level.
    • 从存储器读取数据的存储器访问装置,包括输入地址信息的终端的存储器,输入了以预定周期改变的时钟信号的终端,读取命令被输入的终端,以及终端 根据读取命令,在时钟信号从一个电平变化到另一个电平的定时,输出存储在由地址信息识别的地址的数据,该存储器访问装置包括:地址信息输出单元,其输出地址信息 以及所述读取命令在所述时钟信号从所述一个级别改变到另一个级别的第一定时; 以及读取数据存储单元,其在时钟信号从一个电平变化到另一个电平的第一定时之后的第二定时存储从存储器输出的数据,读取数据存储单元在第二时间之后的第三定时存储数据 时钟信号从一个电平变化到另一个电平的时序。