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51. 发明授权

US06281584B1 Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces 有权
标题翻译：集成电路，具有改善导电和电介质表面界面之间的粘附性
公开(公告)号：US06281584B1
公开(公告)日：2001-08-28
申请号：US09373482
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L2348
CPC分类号： H01L21/31629 , H01L21/76801 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中SiOF电介质层包括其一个边缘处的第一区域，该第一区域耗尽氟到预定深度。

52. 发明授权

US6124640A Scalable and reliable integrated circuit inter-level dielectric 有权
标题翻译：可扩展和可靠的集成电路级间电介质
公开(公告)号：US6124640A
公开(公告)日：2000-09-26
申请号：US144506
申请日：1998-08-31
申请人： Kashmir Sahota , Richard J. Huang , Hung-Sheng Chen , Yu Sun
发明人： Kashmir Sahota , Richard J. Huang , Hung-Sheng Chen , Yu Sun
IPC分类号： H01L21/3105 , H01L21/314 , H01L21/316 , H01L21/768 , H01L51/00
CPC分类号： H01L21/76837 , H01L21/76834 , H01L21/31051 , H01L21/3145 , H01L21/31612
摘要： An inter-level dielectric (ILD) is formed from a lower barrier layer comprising a conformal silicon oxynitride layer, a gap fill layer comprising a high-density plasma (HDP) oxide and a cap layer. The use of HDP oxide as a gap fill layer enables better control of the ILD thickness, avoids outgasing problems, facilitates via formation and reduces planarization.
摘要翻译：层间电介质（ILD）由包括保形氮氧化硅层的下阻挡层，包含高密度等离子体（HDP）氧化物和盖层的间隙填充层形成。使用HDP氧化物作为间隙填充层能够更好地控制ILD厚度，避免出现问题，便于通孔形成并减少平坦化。

53. 发明授权

US6060741A Stacked gate structure for flash memory application 有权
标题翻译：闪存应用的堆叠门结构
公开(公告)号：US6060741A
公开(公告)日：2000-05-09
申请号：US154072
申请日：1998-09-16
申请人： Richard J. Huang
发明人： Richard J. Huang
IPC分类号： H01L29/423 , H01L21/8247 , H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： H01L29/42324
摘要： In order to form a low resistance gate for use in a flash EPROM or EEPROM, a boron doped amorphous silicon layer is formed on an oxide layer and a layer of tungsten nitride formed thereon. A layer of tungsten silicide is then formed on the tungsten nitride layer acts as a barrier preventing "out diffusion" of a contaminating dopant, e.g., boron, and exhibits good adhesion to the amorphous silicon layer. The tungsten silicide layer, in turn, exhibits good adhesion to the tungsten nitride layer thereby preventing lifting of the silicide layer and dopant penetration.
摘要翻译：为了形成用于闪存EPROM或EEPROM的低电阻栅极，在氧化物层和形成在其上的氮化钨层上形成硼掺杂非晶硅层。然后在氮化钨层上形成硅化钨层作为防止污染掺杂剂例如硼的“扩散”的屏障，并且对非晶硅层表现出良好的粘合性。硅化钨层又对氮化钨层表现出良好的粘附性，从而防止了硅化物层的提升和掺杂物的渗透。

54. 发明授权

US5843836A Tunneling technology for reducing intra-conductive layer capacitance 失效
标题翻译：用于降低导电层电容的隧道技术
公开(公告)号：US5843836A
公开(公告)日：1998-12-01
申请号：US744655
申请日：1996-11-06
申请人： Robin W. Cheung , Simon S. Chan , Richard J. Huang
发明人： Robin W. Cheung , Simon S. Chan , Richard J. Huang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/441
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002
摘要： The control speed of semiconductor circuitry is increased by forming air tunnels in the interwiring spaces of a conductive pattern to reduce intra-conductive layer capacitance.
摘要翻译：通过在导电图案的布线间隙中形成空气隧道以减少导电层电容来增加半导体电路的控制速度。

55. 发明授权

US06489230B1 Integration of low-k SiOF as inter-layer dielectric 失效
标题翻译：将低k SiOF作为层间电介质的集成
公开(公告)号：US06489230B1
公开(公告)日：2002-12-03
申请号：US09886032
申请日：2001-06-22
申请人： Richard J. Huang
发明人： Richard J. Huang
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/02131 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/31629 , H01L21/76801 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device formed on a substrate includes at least one metal stack formed on the substrate. A fluorosilicate glass layer is formed on the at least one metal stack, where the fluorosilicate glass layer acts as an interlayer dielectric for the semiconductor device. The fluorosilicate glass layer includes a fluorine-depleted layer at a top portion of the fluorosilicate glass layer that is further away from the substrate. The fluorine-depleted layer is formed by treating the fluorosilicate glass layer with a hydrogen plasma, such as an H2/N2 plasma. The fluorine-depleted layer lessens a likelihood of fluorine atoms in the fluorosilicate glass layer from moving into and thereby corrupting a conducting layer formed above the fluorosilicate glass layer.
摘要翻译：形成在基板上的半导体器件包括形成在基板上的至少一个金属堆叠。在至少一个金属叠层上形成氟硅酸盐玻璃层，其中氟硅酸盐玻璃层用作半导体器件的层间电介质。氟硅酸盐玻璃层包括位于氟硅酸盐玻璃层的远离衬底的顶部的氟耗尽层。通过用诸如H 2 / N 2等离子体的氢等离子体处理氟硅酸盐玻璃层来形成氟耗层。氟耗层降低了氟硅酸盐玻璃层中的氟原子的迁移，从而腐蚀在氟硅酸盐玻璃层上形成的导电层的可能性。

56. 发明授权

US06444593B1 Surface treatment of low-K SiOF to prevent metal interaction 有权
标题翻译：表面处理低K SiOF以防止金属相互作用
公开(公告)号：US06444593B1
公开(公告)日：2002-09-03
申请号：US09373483
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L21425
CPC分类号： H01L21/31629 , H01L21/02131 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/76801 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF电介质层包括其一个边缘处的第一区域，所述第一区域耗尽氟至预定深度。

57. 发明授权

US06335273B2 Surface treatment of low-K SiOF to prevent metal interaction 有权
标题翻译：表面处理低K SiOF以防止金属相互作用
公开(公告)号：US06335273B2
公开(公告)日：2002-01-01
申请号：US09443376
申请日：1999-11-19
申请人： Richard J. Huang , Guarionex Morales , Simon Chan
发明人： Richard J. Huang , Guarionex Morales , Simon Chan
IPC分类号： H01L214763
CPC分类号： H01L21/02131 , H01L21/0214 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/31629 , H01L23/5329 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。进一步优选的是，处理过的表面被钝化。本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟到预定深度。

58. 发明授权

US06271120B1 Method of enhanced silicide layer for advanced metal diffusion barrier layer application 失效
标题翻译：用于先进金属扩散阻挡层应用的增强硅化物层的方法
公开(公告)号：US06271120B1
公开(公告)日：2001-08-07
申请号：US08402252
申请日：1995-03-10
申请人： Richard J. Huang , Robin W. Cheung
发明人： Richard J. Huang , Robin W. Cheung
IPC分类号： H01L214763
CPC分类号： H01L21/76867 , H01L21/76843
摘要： A rapid thermal anneal (>600° C.) in a nitrogen-containing atmosphere is used to form a barrier TiN layer at the bottom of contact openings. To form source and drain contacts, contact openings are etched in a dielectric down to a titanium silicide layer on top of doped regions in the semiconductor (i.e. polysilicon or doped regions in the semiconductor substrate). The barrier TiN layer on the bottom of the contact openings is provided by a rapid thermal anneal in a nitrogen-containing atmosphere which converts the top part of the titanium silicide layer in the contact openings into a barrier TiN layer. This nitrogen-containing atmosphere contains nitrogen-containing species (e.g., N2, NH3, N2O) that react with titanium silicide to form TiN under the conditions provided by the rapid thermal anneal.
摘要翻译：在含氮气氛中的快速热退火（> 600℃）用于在接触开口的底部形成阻挡层TiN层。为了形成源极和漏极触点，在电介质中将接触开口蚀刻到半导体中的掺杂区域（即半导体衬底中的多晶硅或掺杂区域）顶部的硅化钛层。通过在含氮气氛中的快速热退火来提供接触开口底部的阻挡层TiN层，其将接触开口中的硅化钛层的顶部转化为势垒TiN层。该含氮气氛含有与硅化钛反应形成TiN的含氮物质（例如，N 2，NH 3，N 2 O），在快速热退火条件下

59. 发明授权

US06177364B1 Integration of low-K SiOF for damascene structure 有权
标题翻译：用于镶嵌结构的低K SiOF的集成
公开(公告)号：US06177364B1
公开(公告)日：2001-01-23
申请号：US09203754
申请日：1998-12-02
申请人： Richard J. Huang
发明人： Richard J. Huang
IPC分类号： H01L2131
CPC分类号： H01L21/02131 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/31629 , H01L21/76807
摘要： An interlayer dielectric for a damascene structure includes a first etch stop layer formed on a substrate. A first interlayer dielectric layer containing fluorine is formed on the first etch stop layer by deposition. A second etch stop layer is formed on the first interlayer dielectric layer. A second interlayer dielectric layer containing fluorine is formed on the second etch stop layer by deposition. The first and second interlayer dielectric layers and the first and second etch stop layers are etched to form at least one trench and at least one via. The at least one trench and the at least one via are treated with an H2/N2 plasma in-situ, wherein a fluorine-depleted region in the first and second interlayer dielectric layers is formed, and wherein a nitrided region is formed adjacent the fluorine-depleted region, with the nitrided region corresponding to a side surface of the at least one trench and the at least one via. A barrier metal layer is deposited in the at least one trench and the at least one via, whereby the nitrided region provides a passivation layer by which fluorine in the fluorine-depleted region is kept from leeching into the barrier metal layer. The at least one trench and the at least one via are then filled with either copper or aluminum.
摘要翻译：用于镶嵌结构的层间电介质包括形成在基板上的第一蚀刻停止层。通过沉积在第一蚀刻停止层上形成含有氟的第一层间介质层。在第一层间介质层上形成第二蚀刻停止层。通过沉积在第二蚀刻停止层上形成含氟的第二层间介质层。蚀刻第一和第二层间电介质层以及第一和第二蚀刻停止层以形成至少一个沟槽和至少一个通孔。所述至少一个沟槽和所述至少一个通孔在原位处用H 2 / N 2等离子体处理，其中形成所述第一和第二层间电介质层中的氟耗尽区，并且其中邻近所述氟形成氮化区所述氮化区域对应于所述至少一个沟槽和所述至少一个通孔的侧表面。在所述至少一个沟槽和所述至少一个通孔中沉积阻挡金属层，由此所述氮化区域提供钝化层，通过所述钝化层，所述钝化层中的氟贫乏区域中的氟不被浸入所述阻挡金属层。然后用铜或铝填充至少一个沟槽和至少一个通孔。

60. 发明授权

US6124201A Method for manufacturing semiconductors with self-aligning vias 失效
标题翻译：具有自对准通孔的半导体制造方法
公开(公告)号：US6124201A
公开(公告)日：2000-09-26
申请号：US097126
申请日：1998-06-12
申请人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
发明人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
IPC分类号： H01L21/60 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76802
摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. He stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.
摘要翻译：具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。他停止氮化物层是以矩形通孔结构蚀刻氮化物，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

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