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51. 发明授权

US5761691A Linearly addressable microprocessor cache 失效
标题翻译：线性可寻址微处理器缓存
公开(公告)号：US5761691A
公开(公告)日：1998-06-02
申请号：US780263
申请日：1997-01-08
申请人： David B. Witt
发明人： David B. Witt
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1063
摘要： A microprocessor conforming to the X86 architecture is disclosed which includes a linearly addressable cache, thus allowing the cache to be quickly accessed by an external bus while allowing fast translation to a logical address for operation with functional units of microprocessor. Also disclosed is a microprocessor which includes linear tag array and a physical tag array corresponding to the linear tag array, thus allowing the contents of a microprocessor cache to be advantageously monitored from an external bus without slowing the main instruction and data access processing paths.
摘要翻译：公开了符合X86架构的微处理器，其包括线性可寻址高速缓存，从而允许通过外部总线快速访问高速缓存，同时允许快速转换为逻辑地址以与微处理器的功能单元一起操作。还公开了一种微处理器，其包括对应于线性标签阵列的线性标签阵列和物理标签阵列，从而允许从外部总线有利地监视微处理器高速缓存的内容，而不会减慢主指令和数据访问处理路径。

52. 发明授权

US5689672A Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions 失效
标题翻译：预解码指令高速缓存及其方法特别适用于可变字节长度指令
公开(公告)号：US5689672A
公开(公告)日：1997-11-18
申请号：US145905
申请日：1993-10-29
申请人： David B. Witt , Michael D. Goddard
发明人： David B. Witt , Michael D. Goddard
IPC分类号： G06F12/08 , G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F12/00
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/30174 , G06F9/3816
摘要： An instruction cache for a superscalar processor having a variable byte-length instruction format, such as the X86 format, is organized as a 16K byte 4-way set-associative cache. An instruction store array is organized as 1024 blocks of 16 predecoded instruction bytes. The instruction bytes are prefetched and predecoded to facilitate the subsequent parallel decoding and mapping of up to four instructions into a sequence of one or more internal RISC-like operations (ROPs), and the parallel dispatch of up to 4 ROPs by an instruction decoder. Predecode bits are assigned to each instruction byte and are stored with the corresponding instruction byte in the instruction store array. The predecode bits include bits for identifying the starting, ending, and opcode bytes, and for specifying the number of ROPs that an instruction maps into. An address tag array is dual-ported and contains 1024 entries, each composed of a 20-bit address tag, a single valid bit for the entire block, and 16 individual byte-valid bits, one for each of the 16 corresponding instruction bytes within the instruction store array. A successor array is dual-ported and contains 1024 entries, each composed of a 14-bit successor index, a successor valid bit which indicates that the successor index stored in the successor array should be used to access the instruction store array or that no branch is predicted taken within the instruction block, and a block branch index which indicates the byte location within the current instruction block of the last instruction byte predicted to be executed.
摘要翻译：具有诸如X86格式的可变字节长度指令格式的超标量处理器的指令高速缓存被组织为16K字节的4向组关联高速缓存。指令存储阵列被组织为1024个16个预解码指令字节的块。指令字节被预取和预解码，以便于将多达四条指令的后续并行解码和映射到一个或多个内部类似RISC的操作（ROP）的序列中，并且由指令解码器并行调度多达4个ROP。预解码位分配给每个指令字节，并与指令存储阵列中的相应指令字节一起存储。预解码位包括用于标识开始，结束和操作码字节的位，以及用于指定指令映射到的ROP的数量。地址标签阵列是双端口的，包含1024个条目，每个条目由20位地址标签，整个块的单个有效位和16个单独的字节有效位组成，每个字节有效位为16个对应的指令字节指令存储阵列。后继数组是双端口的，包含1024个条目，每个条目由14位后继索引组成，后继有效位表示存储在后继数组中的后继索引应用于访问指令存储阵列或不分支预测在指令块内被预测，以及块分支索引，其指示预测要执行的最后指令字节的当前指令块内的字节位置。

53. 发明授权

US5651125A High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations 失效
标题翻译：高性能超标量微处理器包括通用重排序缓冲器和用于整数和浮点运算的公用寄存器文件
公开(公告)号：US5651125A
公开(公告)日：1997-07-22
申请号：US501243
申请日：1995-07-10
申请人： David B. Witt , William M. Johnson
发明人： David B. Witt , William M. Johnson
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38 , G06F15/167
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30174 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3822 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.
摘要翻译：提供了一种超标量微处理器，其包括共享高性能主数据处理总线的整数功能单元和浮点功能单元。整数单元和浮点单元还共享共同的重排序缓冲器，寄存器文件，分支预测单元和所有驻留在同一主数据处理总线上的加载/存储单元。指令和数据高速缓存通过处理其间的通信的内部地址数据总线耦合到主存储器。指令解码器耦合到指令高速缓存，并且能够每个微处理器周期解码多个指令。指令以推测顺序从解码器发出，发出无序，完成无序。指令从重新排序缓冲区中重新排序到寄存器文件。微处理器的功能单元期望地容纳显示多个数据宽度的操作数。通过所公开的超标量微处理器的共享架构来实现微处理器管芯尺寸的高性能和高效率的使用。

54. 发明授权

US5623627A Computer memory architecture including a replacement cache 失效
标题翻译：计算机内存架构，包括替换缓存
公开(公告)号：US5623627A
公开(公告)日：1997-04-22
申请号：US164246
申请日：1993-12-09
申请人： David B. Witt
发明人： David B. Witt
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0804 , Y02B60/1225
摘要： A microprocessor is provided with an integral, two level cache memory architecture. The microprocessor includes a microprocessor core and a set associative first level cache both located on a common semiconductor die. A replacement cache, which is at least as large as approximately one half the size of the first level cache, is situated on the same semiconductor die and is coupled to the first level cache. In the event of a first level cache miss, a first level entry is discarded and stored in the replacement cache. When such a first level cache miss occurs, the replacement cache is checked to see if the desired entry is stored therein. If a replacement cache hit occurs, then the hit entry is forwarded to the first level cache and stored therein. If a cache miss occurs in both the first level cache and the replacement cache, then a main memory access is commenced to retrieve the desired entry. In that event, the desired entry retrieved from main memory is forwarded to the first level cache and stored therein. When a replacement cache entry is removed from the replacement cache by the replacement algorithm associated therewith, that entry is written back to main memory if that entry was modified. Otherwise the entry is discarded.
摘要翻译：微处理器具有集成的两级缓存存储器架构。微处理器包括位于公共半导体管芯上的微处理器核心和集合关联第一级高速缓存器。至少等于第一级高速缓存大约一半的替换高速缓存位于相同的半导体管芯上，并且耦合到第一级高速缓存。在第一级缓存未命中的情况下，丢弃第一级条目并将其存储在替换高速缓存中。当发生这样的第一级高速缓存未命中时，检查替换高速缓存以查看所需条目是否存储在其中。如果发生替换高速缓存命中，则命中条目转发到第一级缓存并存储在其中。如果在第一级缓存和替换高速缓存中发生高速缓存未命中，则开始主存储器访问以检索所需的条目。在这种情况下，从主存储器检索到的期望条目被转发到第一级缓存并存储在其中。当通过与其相关联的替换算法从替换高速缓存中移除替换高速缓存条目时，如果该条目被修改，则该条目被写回到主存储器。否则丢弃该条目。

55. 发明授权

US5157780A Master-slave checking system 失效
标题翻译：主从检查系统
公开(公告)号：US5157780A
公开(公告)日：1992-10-20
申请号：US536884
申请日：1990-06-12
申请人： Brett B. Stewart , David B. Witt , Bo A. Molander
发明人： Brett B. Stewart , David B. Witt , Bo A. Molander
IPC分类号： G06F11/16 , G06F11/267
CPC分类号： G06F11/1637 , G06F11/2215
摘要： The system comprises a pair of error checking processors connected in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on the inputs to produce mimicked outputs, compares the mimicked outputs with the master outputs and indicates an error condition if the mimicked outputs do not equal the master outputs. A checking circuit forces a difference between the mimicked output and the master output and determines if the master slave configuration accurately determines the presence of the forced error.

56. 发明授权

US06393549B1 Instruction alignment unit for routing variable byte-length instructions 失效
标题翻译：用于路由可变字节长度指令的指令对齐单元
公开(公告)号：US06393549B1
公开(公告)日：2002-05-21
申请号：US09468693
申请日：1999-12-21
申请人： Thang Tran , David B. Witt
发明人： Thang Tran , David B. Witt
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3822
摘要： An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accomodating very high frequencies of operation. In one embodiment, the superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line. The issue position or positions to which an instruction may be dispatched is limited depending upon the position of the instruction's start byte within a line. By limiting the number of issue positions to which a given instruction within a line may be dispatched, the number of cascaded levels of logic required to implement the instruction alignment unit may be advantageously reduced.
摘要翻译：提供了一种指令对准单元，其能够将可变字节长度指令同时路由到在超标量微处理器内形成固定发行位置的多个解码单元。指令对准单元可以用相对较少数量的级联的逻辑门来实现，从而适应非常高的操作频率。在一个实施例中，超标量微处理器包括用于存储多个可变字节长度指令的指令高速缓存器和用于生成识别每个可变字节长度指令的起始字节的位置的预解码标签的预解码单元。指令对准单元被配置为根据其对应的开始字节在高速缓存行中的位置，将多个可变字节长度指令同时传送到预定的发行位置。可以根据指令的起始字节在一行内的位置来限制可以调度指令的问题位置或位置。通过限制可以调度一行中的给定指令的发布位置的数量，可以有利地减少实现指令对准单元所需的逻辑级联级数。

57. 发明授权

US06332191B1 System for canceling speculatively fetched instructions following a branch mis-prediction in a microprocessor 有权
标题翻译：用于在微处理器中的分支误预测之后取消推测取指令的系统
公开(公告)号：US06332191B1
公开(公告)日：2001-12-18
申请号：US09233259
申请日：1999-01-19
申请人： David B. Witt
发明人： David B. Witt
IPC分类号： G06F932
CPC分类号： G06F9/3806 , G06F9/30149 , G06F9/322 , G06F9/3816 , G06F9/3861
摘要： A line predictor is configured to speculatively fetch instructions following a branch instruction. The line predictor stores a plurality of lines that each contain instruction line information. Each line stored by the line predictor includes a fetch address, information regarding one or more instructions, and one or more next fetch addresses. In response to receiving a fetch address, the line predictor is configured to provide instruction line information corresponding to the one or more instructions located at the fetch address to an alignment unit. The line predictor is also configured to provide a next fetch address associated with the fetch address to an instruction cache for speculative fetching and to a branch prediction unit for a branch prediction. The next fetch address is further fed back into the line predictor to generate the instruction line information associated with it and a subsequent next fetch address. A next fetch address may be the sequential address following the last instruction associated with the instruction line information of the fetch address. If an instruction within the instruction line information of the fetch address is a branch instruction, however, the next fetch address may be the target address of the branch instruction. The branch prediction unit is configured to generate a branch prediction in response to receiving a next fetch address if a branch instruction is detected in the instruction line information of the next fetch address. The branch prediction is then compared to a subsequent next fetch address. If the branch prediction differs from a subsequent next fetch address, operations that were initiated using the subsequent next fetch address are canceled, the subsequent next fetch address is updated in the line predictor, and the updated subsequent next fetch address is refetched.
摘要翻译：行预测器被配置为在分支指令之后推测取指令。行预测器存储多行，每行包含指令行信息。线路预测器存储的每条线路包括提取地址，关于一个或多个指令的信息以及一个或多个下一个提取地址。响应于接收到提取地址，线预测器被配置为向对准单元提供与位于取指址处的一个或多个指令相对应的指令行信息。线预测器还被配置为提供与获取地址相关联的下一个提取地址到用于推测性提取的指令高速缓存以及用于分支预测的分支预测单元。下一个提取地址被进一步反馈到行预测器中以生成与其相关联的指令行信息和随后的下一个提取地址。下一个提取地址可以是与取出地址的指令行信息相关联的最后指令之后的顺序地址。然而，如果提取地址的指令行信息内的指令是分支指令，则下一个提取地址可以是分支指令的目标地址。如果在下一个提取地址的指令行信息中检测到转移指令，则分支预测单元被配置为响应于接收到下一个获取地址而生成分支预测。然后将分支预测与随后的下一个提取地址进行比较。如果分支预测与随后的下一个提取地址不同，则使用随后的下一个提取地址发起的操作被取消，随后的下一个提取地址在行预测器中被更新，并且更新后续的下一个提取地址被重新获取。

58. 发明授权

US06298423B1 High performance load/store functional unit and data cache 失效
标题翻译：高性能加载/存储功能单元和数据缓存
公开(公告)号：US06298423B1
公开(公告)日：2001-10-02
申请号：US08703299
申请日：1996-08-26
申请人： William M. Johnson , David B. Witt , Murali Chinnakonda
发明人： William M. Johnson , David B. Witt , Murali Chinnakonda
IPC分类号： G06F1202
CPC分类号： G06F9/30043 , G06F9/3816 , G06F9/3826 , G06F9/3834 , G06F9/3836
摘要： A load/store functional unit and a corresponding data cache of a superscalar microprocessor is disclosed. The load/store functional unit includes a plurality of reservation station entries which are accessed in parallel and which are coupled to the data cache in parallel. The load/store functional unit also includes a store buffer circuit having a plurality of store buffer entries. The store buffer entries are organized to provide a first in first out buffer where the outputs from less significant entries of the buffer are provided as inputs to more significant entries of the buffer.
摘要翻译：公开了超标量微处理器的加载/存储功能单元和对应的数据高速缓存。加载/存储功能单元包括并行访问并且并行耦合到数据高速缓存的多个保留站条目。加载/存储功能单元还包括具有多个存储缓冲器条目的存储缓冲器电路。存储缓冲器条目被组织以提供先进先出的缓冲器，其中来自缓冲器的较不重要条目的输出被提供作为缓冲器的更重要条目的输入。

59. 发明授权

US06212622B1 Mechanism for load block on store address generation 有权
标题翻译：存储地址生成时加载块的机制
公开(公告)号：US06212622B1
公开(公告)日：2001-04-03
申请号：US09138886
申请日：1998-08-24
申请人： David B. Witt
发明人： David B. Witt
IPC分类号： G06F938
CPC分类号： G06F9/3814 , G06F9/30043 , G06F9/30087 , G06F9/30145 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3869
摘要： A processor employs ordering dependencies for load instruction operations upon store address instruction operations. The processor divides store operations into store address instruction operations and store data instruction operations. The store address instruction operations generate the address of the store, and the store data instruction operations route the corresponding data to the load/store unit. The processor maintains a store address dependency vector indicating each of the outstanding store addresses and records ordering dependencies upon the store address instruction operations for each load instruction operation. Accordingly, the load instruction operation is not scheduled until each prior store address instruction operation has been scheduled. Store addresses are available for dependency checking against the load address upon execution of the load instruction operation. If a memory dependency exists, it may be detected upon execution of the load instruction operation.
摘要翻译：处理器在存储地址指令操作时对加载指令操作采用排序依赖。处理器将存储操作分为存储地址指令操作和存储数据指令操作。存储地址指令操作生成存储器的地址，并且存储数据指令操作将对应的数据路由到加载/存储单元。处理器维护指示每个未完成存储地址的存储地址相关性向量，并且对每个加载指令操作的存储地址指令操作记录排序依赖性。因此，在调度每个先前的存储地址指令操作之前，不调度加载指令操作。在执行加载指令操作时，存储地址可用于对负载地址的依赖性检查。如果存在存储器依赖性，则可以在执行加载指令操作时检测到它。

60. 发明授权

US06189087B1 Superscalar instruction decoder including an instruction queue 失效
标题翻译：超标量指令解码器包括指令队列
公开(公告)号：US06189087B1
公开(公告)日：2001-02-13
申请号：US08906730
申请日：1997-08-05
申请人： David B. Witt , Michael D. Goddard
发明人： David B. Witt , Michael D. Goddard
IPC分类号： G06F938
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/30152 , G06F9/30174 , G06F9/3816 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A superscalar complex instruction set computer (“CISC”) processor having a reduced instruction set computer (“RISC”) superscalar core includes an instruction cache which identifies and marks raw x86 instruction start and end points and encodes “pre-decode” information, a byte queue which is a queue of aligned instruction and pre-decode information of the “predicted executed” state, and an instruction decoder which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue and determines the number of possible x86 instruction dispatch for shifting the byte que. The instruction decoder includes in each dispatch position a logic conversion path, a memory conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer directs x86 instructions from the byte queue to the conversion paths, a select circuit assembles ROP information from the appropriate conversion paths, and a shared circuit processes ROP information from the select circuit for shared resources. ROP type and opcode information is dispatched from the instruction decoder to the RISC core. Pointers to the A and B source operands are furnished by the instruction decoder to a register file and to a reorder buffer in the RISC core, which in turn furnish the appropriate “predicted executed” versions of the A and B operands to various functional units in the RISC core in coordination with the ROP type and opcode information.
摘要翻译：具有精简指令集计算机（“RISC”）超标量核的超标量复合指令集计算机（“CISC”）处理器包括：指令高速缓存，用于识别并标记原始x86指令开始和结束点，并对“预解码”信息进行编码，作为“预测执行”状态的对准指令队列和预解码信息的字节队列，以及基于对齐的预处理生成类RISC操作（ROP）的类型，操作码和操作数指针值的指令解码器，在字节队列中解码x86指令，并确定可能的x86指令调度数，用于移位字节que。指令解码器在每个调度位置包括逻辑转换路径，存储器转换路径和用于将CISC指令转换为ROP的公共转换路径。 ROP多路复用器将x86指令从字节队列引导到转换路径，选择电路从适当的转换路径组装ROP信息，共享电路从共享资源的选择电路处理ROP信息。 ROP类型和操作码信息从指令解码器发送到RISC内核。指向A和B源操作数的指针由指令解码器提供给寄存器文件，并提供给RISC内核中的重排序缓冲器，RISC内核又将A和B操作数的适当“预测执行”版本提供给各种功能单元 RISC核心与ROP类型和操作码信息协调。

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