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51. 发明申请

US20120191392A1 METHOD FOR ANALYZING CORRELATIONS AMONG DEVICE ELECTRICAL CHARACTERISTICS AND METHOD FOR OPTIMIZING DEVICE STRUCTURE 审中-公开
标题翻译：用于分析装置电气特性中的相关性的方法和用于优化装置结构的方法
公开(公告)号：US20120191392A1
公开(公告)日：2012-07-26
申请号：US13321684
申请日：2011-08-10
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： G06F19/00 , G01R27/00 , G01R19/00
CPC分类号： G06F17/5045 , G01R31/2846 , G06F2217/08 , H01L22/20
摘要： A method for analyzing correlations among electrical characteristics of an electronic device and a method for optimizing a structure of the electronic device are disclosed. The electronic device may comprises a plurality of electrical characteristics v1, v2, v3, . . . , vm, wherein the electrical characteristics v2, v3, . . . . , vm constitute a (m−1) dimensional space. For a plurality of discrete measurement points (v2k, v3k, . . . , vmk) in the (m−1) dimensional space, a plurality of corresponding measurement values of the electrical characteristic v1 has already been obtained. The method comprises: performing a Delaunay triangulation operation on the plurality of measurement points (v2k, v3k, . . . , vmk) in the (m−1) dimensional space; calculating a plurality of interpolation values of the electrical characteristic v1 corresponding to a plurality of interpolation points (v2i, v3i, . . . , vmi) by means of interpolation based on the result of the Delaunay triangulation operation; and determining the correlation between the electrical characteristics v1 and v2 from the plurality of measurement points and the plurality of interpolation points as well as the plurality of corresponding measurement values and the plurality of corresponding interpolation values.
摘要翻译：公开了一种用于分析电子设备的电特性之间的相关性的方法和用于优化电子设备的结构的方法。电子设备可以包括多个电气特征v1，v2，v3，...。。。，vm，其中电特性v2，v3，...，。。。，vm构成（m-1）维空间。对于（m-1）维空间中的多个离散测量点（v2k，v3k，...，vmk），已经获得了电特性v1的多个对应的测量值。该方法包括：对（m-1）维空间中的多个测量点（v2k，v3k，...，vmk）执行德劳内三角测量操作; 通过基于Delaunay三角测量运算结果的插值计算与多个插值点（v2i，v3i，...，vmi）对应的电特性v1的多个内插值; 以及确定来自所述多个测量点和所述多个内插点的电特性v1和v2之间的相关性以及所述多个对应的测量值和所述多个对应的内插值。

52. 发明申请

US20120112358A1 STACK-TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：堆叠型半导体器件及其制造方法
公开(公告)号：US20120112358A1
公开(公告)日：2012-05-10
申请号：US13120792
申请日：2011-02-17
申请人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.
摘要翻译：堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合通过导电通孔。这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高可靠性的三维半导体器件。

53. 发明申请

US20120091514A1 Semiconductor Junction Diode Device And Method For Manufacturing The Same 审中-公开
标题翻译：半导体结二极管器件及其制造方法
公开(公告)号：US20120091514A1
公开(公告)日：2012-04-19
申请号：US13377958
申请日：2011-02-27
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/8611 , H01L29/1602 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/6603 , H01L29/6606 , H01L29/6609 , H01L29/66128 , H01L29/66204 , H01L29/861
摘要： A semiconductor junction diode device structure and a method for manufacturing the same are provided, where a gate of the diode device structure is directly formed on the substrate, a P-N junction is formed in the semiconductor substrate, a first contact is formed on the gate, and a second contact is formed on the doped region at both sides of the gate, the first contact and the second contact acting as cathode/anode of the diode device, respectively. The diode device of this structure occupies a small area, and its forming process may be integrated in a gate-last integration process of MOSFET devices, which needs no additional mask and costs and has a high integration level.
摘要翻译：提供一种半导体结二极管器件结构及其制造方法，其中二极管器件结构的栅极直接形成在衬底上，在该半导体衬底中形成PN结，在栅极上形成第一接触，并且第二接触形成在栅极两侧的掺杂区域上，第一接触和第二接触分别用作二极管器件的阴极/阳极。该结构的二极管器件占地面积小，其形成过程可集成在MOSFET器件的最终集成过程中，无需额外的掩模和成本，并具有较高的集成度。

54. 发明授权

US08716799B2 MOSFET 有权
公开(公告)号：US08716799B2
公开(公告)日：2014-05-06
申请号：US13376996
申请日：2011-08-01
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/78648 , H01L21/2652
摘要： The present application discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer, which comprises a semiconductor substrate, a buried insulator layer, and a semiconductor layer, the buried insulator layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulator layer; a gate stack, which is disposed on the semiconductor layer; a source region and a drain region, which are disposed in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which are disposed in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate disposed in the semiconductor substrate, and wherein the back gate comprises first, second and third compensation doping regions, the first compensation doping region is disposed under the source region and the drain region; the second compensation doping region extends in a direction away from the channel region and adjoining the first compensation doping region; and the third compensation doping region is disposed under the channel region and adjoining the first compensation doping region. By changing the doping type of the back gate, the MOSFET can have an adjustable threshold voltage, and can have a reduced parasitic capacitance and a reduced contact resistance in connection with the back gate.
摘要翻译：本申请公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体基板，埋入绝缘体层和半导体层，所述埋入绝缘体层设置在所述半导体基板上，并且所述半导体层设置在所述埋入绝缘体层上; 栅极堆叠，其设置在半导体层上; 源极区域和漏极区域，其设置在所述半导体层中并且在所述栅极堆叠的相对侧上; 以及沟道区域，其设置在所述半导体层中并且被所述源极区域和所述漏极区域夹持，其中所述MOSFET还包括设置在所述半导体衬底中的背栅极，并且其中所述后栅极包括第一，第二和第三补偿掺杂第一补偿掺杂区域设置在源极区域和漏极区域下方; 所述第二补偿掺杂区域在远离所述沟道区域并邻接所述第一补偿掺杂区域的方向上延伸; 并且第三补偿掺杂区域设置在沟道区域的下方并与第一补偿掺杂区域相邻。通过改变背栅的掺杂类型，MOSFET可以具有可调的阈值电压，并且可以具有减小的寄生电容和与后栅极相关联的降低的接触电阻。

55. 发明授权

US09252280B2 MOSFET and method for manufacturing the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US09252280B2
公开(公告)日：2016-02-02
申请号：US13510461
申请日：2011-11-18
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66
CPC分类号： H01L29/78648 , H01L29/66742 , H01L29/78609
摘要： The present disclosure discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. The MOSFET includes: a silicon on insulator (SOI) wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate.
摘要翻译：本公开公开了一种金属氧化物半导体场效应晶体管（MOSFET）及其制造方法。所述MOSFET包括：绝缘体上硅（SOI）晶片，其包含半导体衬底，掩埋绝缘层和半导体层，所述掩埋绝缘层位于所述半导体衬底上，所述半导体层位于所述掩埋绝缘层上; 半导体层上的栅极堆叠; 源极区域和漏极区域，其位于半导体层中并且在栅极堆叠的相对侧上; 以及沟道区，其位于所述半导体层中并且被所述源极区和所述漏极区夹持，其中所述MOSFET还包括背栅极，所述后栅极位于所述半导体衬底中，并且在所述半导体衬底的下部具有第一掺杂区域的背栅极和在后栅极的上部中的第二掺杂区域。

56. 发明申请

US20130001665A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130001665A1
公开(公告)日：2013-01-03
申请号：US13379433
申请日：2011-08-02
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/78648
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate.
摘要翻译：本公开公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体基板，埋入绝缘层和半导体层，所述埋入绝缘层设置在所述半导体基板上，半导体层设置在掩埋绝缘层上; 设置在半导体层上的栅极堆叠; 源极区域和漏极区域，嵌入在半导体层中并设置在栅极叠层的两侧; 以及嵌入所述半导体层并夹在所述源极区域和所述漏极区域之间的沟道区域，其中所述MOSFET还包括背栅极和反向掺杂区域，并且其中所述背栅极嵌入所述半导体衬底中，所述反掺杂区域设置在沟道区域下方并嵌入在后栅极中，并且背栅极具有与反相掺杂区域相反的掺杂型。 MOSFET可以通过改变背栅极的掺杂类型来调节阈值电压。

57. 发明申请

US20120139048A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： MOSFET及其制造方法
公开(公告)号：US20120139048A1
公开(公告)日：2012-06-07
申请号：US13140744
申请日：2011-03-04
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/42384 , H01L29/4908 , H01L29/66772 , H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI chip comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; source/drain regions formed in the semiconductor layer; a channel region formed in the semiconductor layer and located between the source/drain regions; and a gate stack comprising a gate dielectric layer on the semiconductor layer, and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the semiconductor substrate below the channel region, and the backgate has a non-uniform doping profile, and wherein the buried insulating layer serves as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the type of dopant and/or the doping profile in the backgate, and reduces a leakage current of the semiconductor device.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括SOI芯片，其包括半导体衬底，半导体衬底上的掩埋绝缘层和掩埋绝缘层上的半导体层; 在半导体层中形成的源/漏区; 形成在所述半导体层中且位于所述源/漏区之间的沟道区; 以及栅极堆叠，其包括在所述半导体层上的栅极电介质层和所述栅极介电层上的栅极导体，其中所述MOSFET还包括形成在所述沟道区域下方的所述半导体衬底的一部分中的后栅极， - 均匀的掺杂分布，并且其中所述掩埋绝缘层用作所述背栅的栅极电介质层。通过改变背栅中的掺杂剂类型和/或掺杂分布，MOSFET具有可调节的阈值电压，并且减小了半导体器件的漏电流。

58. 发明授权

US09633854B2 MOSFET and method for manufacturing the same 有权
公开(公告)号：US09633854B2
公开(公告)日：2017-04-25
申请号：US13379433
申请日：2011-08-02
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/265 , H01L29/66 , H01L29/786 , H01L21/26
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/78648
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate.

59. 发明授权

US08933512B2 MOSFET and method for manufacturing the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US08933512B2
公开(公告)日：2015-01-13
申请号：US13208964
申请日：2011-08-12
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L21/336 , H01L29/772 , H01L29/786
CPC分类号： H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI wafer, which comprises a bottom semiconductor substrate, a first buried insulating layer on the bottom semiconductor substrate, and a first semiconductor layer on the first buried insulating layer; a source region and a drain region which are formed in a second semiconductor layer over the SOI wafer, wherein there is a second buried insulating layer between the second semiconductor layer and the SOI wafer; a channel region, which is formed in the second semiconductor layer and located between the source region and the drain regions; and a gate stack, which comprises a gate dielectric layer on the second semiconductor layer and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the first semiconductor substrate below the channel region, the backgate having a non-uniform doping profile, and the second buried insulating layer serving as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the polarity of dopants and/or the doping profile in the backgate. Leakage in the semiconductor device can be reduced.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括SOI晶片，其包括底部半导体衬底，底部半导体衬底上的第一掩埋绝缘层和第一掩埋绝缘层上的第一半导体层; 源极区和漏极区，形成在SOI晶片上的第二半导体层中，其中在第二半导体层和SOI晶片之间存在第二掩埋绝缘层; 沟道区，其形成在所述第二半导体层中并且位于所述源极区和所述漏极区之间; 以及栅极堆叠，其包括在所述第二半导体层上的栅极介电层和所述栅极电介质层上的栅极导体，其中所述MOSFET还包括形成在所述沟道区域下方的所述第一半导体衬底的一部分中的后栅极，不均匀的掺杂分布，以及用作背栅的栅介电层的第二掩埋绝缘层。通过改变背栅中的掺杂剂的极性和/或掺杂分布，MOSFET具有可调节的阈值电压。可以减少半导体器件中的泄漏。

60. 发明申请

US20130099315A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130099315A1
公开(公告)日：2013-04-25
申请号：US13510461
申请日：2011-11-18
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78648 , H01L29/66742 , H01L29/78609
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate. The MOSFET can adjust the threshold voltage by changing the doping type and doping concentration of the anti-doped region.
摘要翻译：本公开公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体基板，埋入绝缘层和半导体层，所述埋入绝缘层位于所述半导体基板上，半导体层位于掩埋绝缘层上; 半导体层上的栅极堆叠; 源极区域和漏极区域，其位于半导体层中并且在栅极堆叠的相对侧上; 以及沟道区，其位于所述半导体层中并且被所述源极区和所述漏极区夹持，其中所述MOSFET还包括背栅极，所述后栅极位于所述半导体衬底中，并且在所述半导体衬底的下部具有第一掺杂区域的背栅极和在后栅极的上部中的第二掺杂区域。 MOSFET可以通过改变反掺杂区域的掺杂浓度和掺杂浓度来调节阈值电压。

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