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51. 发明申请

US20090011716A1 SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：用于可编程逻辑器件高速串行接口的信号丢失检测器
公开(公告)号：US20090011716A1
公开(公告)日：2009-01-08
申请号：US11773234
申请日：2007-07-03
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04Q7/20
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

52. 发明授权

US09224685B1 Shielded metal-oxide-metal (MOM) capacitor structure 有权
标题翻译：屏蔽金属氧化物金属（MOM）电容器结构
公开(公告)号：US09224685B1
公开(公告)日：2015-12-29
申请号：US13416137
申请日：2012-03-09
申请人： Weiqi Ding , Wilson Wong , Shuxian Chen , Jeffrey T. Watt
发明人： Weiqi Ding , Wilson Wong , Shuxian Chen , Jeffrey T. Watt
IPC分类号： H01L23/522 , H01L49/02
CPC分类号： H01L23/5226 , H01L23/522 , H01L23/5223 , H01L23/5225 , H01L28/82 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： A metal-oxide-metal (MOM) capacitor structure is disclosed. The MOM capacitor includes a plurality of layers, each layer having a plurality of electrodes. The plurality of electrodes, separated by oxide layers, forms a first plate and a second plate of the MOM capacitor. The plurality of electrodes on each of the layers is coupled to a plurality of electrodes on an adjacent layer through a plurality of vias. A shield layer is coupled to each of the electrodes that forms the second plate of the MOM capacitor on each of the plurality of layers.
摘要翻译：公开了一种金属氧化物金属（MOM）电容器结构。 MOM电容器包括多个层，每层具有多个电极。由氧化物层分隔开的多个电极形成MOM电容器的第一板和第二板。每个层上的多个电极通过多个通孔耦合到相邻层上的多个电极。屏蔽层耦合到在多个层中的每一层上形成MOM电容器的第二板的每个电极。

53. 发明授权

US08989214B2 High-speed serial data signal receiver circuitry 有权
公开(公告)号：US08989214B2
公开(公告)日：2015-03-24
申请号：US12002539
申请日：2007-12-17
申请人： Weiqi Ding , Mengchi Liu , Wilson Wong , Sergey Shumarayev
发明人： Weiqi Ding , Mengchi Liu , Wilson Wong , Sergey Shumarayev
IPC分类号： H04L12/66 , H04L25/03 , H04L7/00
CPC分类号： H04L25/03885 , H04L7/0054 , H04L25/03019 , H04L25/03878
摘要： Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

54. 发明授权

US08860469B1 Apparatus and methods for transmitter output swing calibration 有权
标题翻译：发射机输出摆幅校准的装置和方法
公开(公告)号：US08860469B1
公开(公告)日：2014-10-14
申请号：US13549228
申请日：2012-07-13
申请人： Weiqi Ding , Wilson Wong
发明人： Weiqi Ding , Wilson Wong
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： G11C29/028 , G11C29/022
摘要： Disclosed are apparatus and methods to advantageously calibrate a transmitter output swing. One embodiment relates to a method for calibrating the output swing voltage of a transmitter. A fixed value is provided as the data input, and output swing calibration circuitry is connected to the transmitter buffer circuit. A transmitter current is set to an initial level, and the transmitter current is adjusted until the output swing of the transmitter buffer circuit is calibrated. Another embodiment relates to an integrated circuit which includes a transmitter buffer circuit, output swing calibration circuitry, and switches arranged to electrically connect the transmitter buffer circuit to the output swing calibration circuitry during an output swing calibration mode. Another embodiment relates to an output swing calibration circuit which includes comparison circuitry and logic and control circuitry.
摘要翻译：公开了有利地校准发射机输出摆幅的装置和方法。一个实施例涉及用于校准发射机的输出摆幅电压的方法。提供固定值作为数据输入，输出摆幅校准电路连接到发送器缓冲电路。发射机电流被设置为初始电平，并且调整发射机电流直到校准发射机缓冲器电路的输出摆幅。另一个实施例涉及一种集成电路，其包括发射器缓冲电路，输出摆幅校准电路和布置成在输出摆幅校准模式期间将发射器缓冲电路电连接到输出摆幅校准电路。另一个实施例涉及一种包括比较电路和逻辑和控制电路的输出摆幅校准电路。

55. 发明授权

US08692582B1 Latched comparator circuitry 有权
标题翻译：锁存比较器电路
公开(公告)号：US08692582B1
公开(公告)日：2014-04-08
申请号：US13345384
申请日：2012-01-06
申请人： Ali Atesoglu , Weiqi Ding
发明人： Ali Atesoglu , Weiqi Ding
IPC分类号： H03K5/22
CPC分类号： H03K3/037 , H03K5/249
摘要： Integrated circuits having analog-to-digital converters are provided. Analog-to-digital converters may contain latched comparators. A latched comparator may include inputs configured to receive a differential input voltage signal, a differential reference voltage signal, and a clock signal. The comparator may include a preamplifier, a latching circuit, a level shifter, and a flip-flop coupled in series. The preamplifier may include large input transistors for minimizing offset, stacked tail transistors, and diode-connected load transistors for minimizing kickback noise. The preamplifier may be used to generate amplified voltage signals. The latching circuit may include a first pair of cross-coupled pull-down transistors, a second pair of cross-coupled pull-up transistors, and precharge transistors. The precharge transistors may serve to precharge the latch output to a predetermined voltage level during a first clock phase, whereas the first and second transistor pairs may serve to perform exponential regeneration on the amplified voltage signals during a second clock phase.
摘要翻译：提供了具有模数转换器的集成电路。模数转换器可能包含锁存的比较器。锁存的比较器可以包括被配置为接收差分输入电压信号，差分参考电压信号和时钟信号的输入。比较器可以包括前置放大器，锁存电路，电平移位器和串联耦合的触发器。前置放大器可以包括用于最小化偏移的堆叠尾部晶体管的大输入晶体管和用于最小化反冲噪声的二极管连接的负载晶体管。前置放大器可用于产生放大的电压信号。锁存电路可以包括第一对交叉耦合下拉晶体管，第二对交叉耦合上拉晶体管和预充电晶体管。预充电晶体管可以用于在第一时钟相位期间将锁存器输出预充电到预定电压电平，而第一和第二晶体管对可用于在第二时钟相位期间对放大的电压信号执行指数再生。

56. 发明授权

US08395421B1 Configurable buffer circuits and methods 有权
标题翻译：可配置缓冲电路和方法
公开(公告)号：US08395421B1
公开(公告)日：2013-03-12
申请号：US13446772
申请日：2012-04-13
申请人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
发明人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
IPC分类号： H03B1/00
CPC分类号： H04L25/0272
摘要： A buffer circuit includes first and second inputs and first and second outputs. The buffer circuit is configurable to buffer a differential input signal received at the first and the second inputs to generate a differential output signal at the first and the second outputs in a current mode logic buffer mode based on a control signal. The buffer circuit is configurable to buffer the differential input signal to generate the differential output signal in an H-bridge buffer mode based on the control signal.
摘要翻译：缓冲电路包括第一和第二输入以及第一和第二输出。缓冲电路可配置为缓冲在第一和第二输入处接收的差分输入信号，以在基于控制信号的当前模式逻辑缓冲器模式中在第一和第二输出处产生差分输出信号。缓冲电路可配置为基于控制信号缓冲差分输入信号以产生H桥缓冲器模式中的差分输出信号。

57. 发明申请

US20130009279A1 INTEGRATED CIRCUITS WITH CONFIGURABLE INDUCTORS 有权
标题翻译：集成电路与配置电感器
公开(公告)号：US20130009279A1
公开(公告)日：2013-01-10
申请号：US13617347
申请日：2012-09-14
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H01L27/08 , H01L21/20
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

58. 发明申请

US20120256670A1 Techniques for Reducing Duty Cycle Distortion in Periodic Signals 有权
标题翻译：降低周期信号占空比变形的技术
公开(公告)号：US20120256670A1
公开(公告)日：2012-10-11
申请号：US13083431
申请日：2011-04-08
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

59. 发明授权

US08228102B1 Phase-locked loop architecture and clock distribution system 有权
标题翻译：锁相环架构和时钟分配系统
公开(公告)号：US08228102B1
公开(公告)日：2012-07-24
申请号：US12717062
申请日：2010-03-03
申请人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
发明人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
IPC分类号： H03L7/06
CPC分类号： H03L7/23 , G06F1/10 , H03L7/0807 , H03L7/183 , H03L7/197 , H03L7/1974 , H04L7/0331
摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条侧。可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。每个PMA三元组模块包括第一，第二和第三通道。第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。还公开了其它实施例和特征。

60. 发明授权

US08188774B1 Apparatus and methods for activation of an interface on an integrated circuit 有权
标题翻译：用于激活集成电路上的接口的装置和方法
公开(公告)号：US08188774B1
公开(公告)日：2012-05-29
申请号：US12833718
申请日：2010-07-09
申请人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
发明人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
IPC分类号： H03L7/00
CPC分类号： H03K19/1774
摘要： One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.
摘要翻译：一个实施例涉及在集成电路的核心变得可操作时激活集成电路上的接口的方法。收发器通道的偏移校准由物理介质连接电路执行。传输频率被收发器通道的发射机锁相环锁定，并且接收频率被收发信机的接收机锁相环锁定。随后，当集成电路的核心部件变得可操作时，该接口被激活。另一实施例涉及包括收发信道电路，接口处理器和复位控制状态机的集成电路。另一实施例涉及包括复位控制状态机，收发信道电路，信道输入转向多路复用器和信道输出转向多路复用器的控制电路。还公开了其它实施例，方面和特征。

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