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51. 发明申请

US20130074878A1 WAFER SCRUBBER 有权
公开(公告)号：US20130074878A1
公开(公告)日：2013-03-28
申请号：US13243315
申请日：2011-09-23
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B7/00
CPC分类号： B08B17/025 , H01L21/67051 , H01L21/6715 , Y10S134/902
摘要： A wafer scrubber is disclosed, including a chamber, and a holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and the wafer spins to remove water on the wafer, and a mashed inner cup comprising a plurality of through holes disposed between the holder and a wall of the chamber, wherein the mashed inner cup receives water from a surface of the wafer and rotates around the spindle to release the water through the through holes.
摘要翻译：公开了一种晶片洗涤器，其包括腔室和连接到设置在腔室中的心轴的保持器，其中保持器支撑晶片，并且晶片旋转以去除晶片上的水，以及捣碎的内杯，其包括多个通孔设置在保持器和室的壁之间的孔，其中，捣碎的内杯从晶片的表面接收水并围绕心轴旋转以通过通孔释放水。

52. 发明授权

US08399321B2 Method for manufacturing memory device 有权
标题翻译：制造存储器件的方法
公开(公告)号：US08399321B2
公开(公告)日：2013-03-19
申请号：US13111745
申请日：2011-05-19
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/425
CPC分类号： H01L27/10867 , H01L21/26586 , H01L27/10873 , H01L29/1083 , H01L29/66659
摘要： The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor.
摘要翻译：提供了一种用于制造存储器件的方法。该方法包括：将第一杂质注入到与栅极导体结构相邻的衬底中，以在栅极导体结构的第一侧上形成源极区，在栅极导体结构的第二侧上形成漏极区; 将第二杂质注入到所述衬底中以形成邻近所述源极区设置的卤素注入区，其中所述晕圈注入区具有不降解所述存储器件的数据保留时间的掺杂浓度; 对所述漏极区进行退火处理，在所述漏极区域下方形成扩散区域，其中，控制所述退火处理的工艺温度，以确保所述扩散区域的掺杂浓度基本上等于保持电连接的阈值浓度在漏极和深沟槽电容器之间。

53. 发明申请

US20130043470A1 CRACK STOP STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：裂缝停止结构及其形成方法
公开(公告)号：US20130043470A1
公开(公告)日：2013-02-21
申请号：US13214227
申请日：2011-08-21
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/544 , H01L21/762 , H01L23/482
CPC分类号： H01L21/76224 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.
摘要翻译：本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

54. 发明申请

US20120289134A1 CMP SLURRY MIX AND DELIVERY SYSTEM 审中-公开
标题翻译： CMP浆液混合和输送系统
公开(公告)号：US20120289134A1
公开(公告)日：2012-11-15
申请号：US13106861
申请日：2011-05-13
申请人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B24B57/00
CPC分类号： B24B57/02 , B24B37/04
摘要： A CMP slurry mix and delivery system includes at least one container for holding a polishing agent; a pump connected to the container for pumping the polishing agent to a point of use; and a slurry dispersion unit installed between the pump and the point of use, wherein slurry dispersion unit provides megasonic energy that is capable of dispersing the polishing agent flowing through the slurry dispersion unit.
摘要翻译： CMP浆料混合和输送系统包括至少一个用于保持抛光剂的容器; 连接到容器以将抛光剂泵送到使用点的泵; 以及安装在泵和使用点之间的浆料分散单元，其中浆料分散单元提供能够分散流过浆料分散单元的抛光剂的兆声波能量。

55. 发明申请

US20120285484A1 METHOD FOR CLEANING A SEMICONDUCTOR WAFER 审中-公开
标题翻译：清洗半导体波形的方法
公开(公告)号：US20120285484A1
公开(公告)日：2012-11-15
申请号：US13106869
申请日：2011-05-13
申请人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B1/00
CPC分类号： H01L21/02052 , B08B1/00 , H01L21/67046
摘要： A wafer cleaning method includes: (1) providing a wafer cleaning apparatus comprising a sponge for scrubbing a surface of a semiconductor wafer to be cleaned; (2) implementing a pre-conditioning flow to pre-condition the sponge using a dummy wafer; and (3) performing a regular cleaning flow to scrub the surface of the semiconductor wafer to be cleaned using the pre-conditioned sponge. The dummy wafer has a plurality of upward protruding features on a surface of the dummy wafer for removing residual fibers or unwanted substances from the sponge.
摘要翻译：晶片清洗方法包括：（1）提供一种晶片清洗装置，其包括用于擦洗要清洗的半导体晶片的表面的海绵; （2）实施预调节流程，以使用虚拟晶片对海绵进行预处理; 和（3）执行常规清洁流程以使用预先调节的海绵擦洗待清洁的半导体晶片的表面。虚拟晶片在虚拟晶片的表面上具有多个向上突出的特征，用于从海绵中除去残留的纤维或不需要的物质。

56. 发明申请

US20120284936A1 POST-CMP WAFER CLEANING APPARATUS 有权
标题翻译：后CMP波形清洗装置
公开(公告)号：US20120284936A1
公开(公告)日：2012-11-15
申请号：US13104964
申请日：2011-05-10
申请人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B1/04
CPC分类号： H01L21/67051 , H01L21/02052 , H01L21/67046
摘要： A post-CMP wafer cleaning apparatus includes a chamber; a plurality of rollers adapted to hold and rotate a wafer within the chamber; at least one brush adapted to scrub a surface of the wafer to be cleaned; and a liquid spraying device adapted to spray a liquid on the wafer, the liquid spraying device comprising two spray bars jointed together via a joint member.
摘要翻译： CMP后晶片清洗装置包括：腔室; 多个辊子，适于在所述腔室内保持和旋转晶片; 至少一个刷子，适于擦拭要清洁的晶片的表面; 以及适于将液体喷射在晶片上的液体喷射装置，所述液体喷射装置包括通过接头构件连接在一起的两个喷射杆。

57. 发明申请

US20120273874A1 MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF 有权
标题翻译：具有BIT线和垂直晶体管的存储器件及其制造方法
公开(公告)号：US20120273874A1
公开(公告)日：2012-11-01
申请号：US13094796
申请日：2011-04-26
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/2257 , H01L27/10876 , H01L27/10885 , H01L29/7827
摘要： A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.
摘要翻译：提供一种形成掩埋位线的方法。提供衬底并且在衬底中限定线状沟槽区域。在基板的线状沟槽区域中形成线状沟槽。线状沟槽包括侧壁表面和底部表面。然后，将线状沟槽的底面加宽，形成弯曲的底面。接下来，在与该弯曲底面相邻的基板上形成掺杂区域。最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。

58. 发明申请

US20120267727A1 METHOD FOR FORMING SELF-ALIGNED CONTACT 有权
标题翻译：形成自对准接触的方法
公开(公告)号：US20120267727A1
公开(公告)日：2012-10-25
申请号：US13093742
申请日：2011-04-25
申请人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L23/485 , H01L21/76897 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.
摘要翻译：具有自对准接触的集成电路包括其上形成有晶体管的衬底，介电间隔物，保护屏障和导电层。晶体管包括掩模层和形成在掩模层的相对侧上的一对绝缘间隔物。电介质间隔物部分地覆盖晶体管的至少一个绝缘间隔物。保护屏障形成在电介质间隔物上。导电层形成在掩模层，保护屏障，电介质间隔物，绝缘间隔物和介电间隔物上，作为用于接触晶体管的源/漏区的自对准接触。

59. 发明授权

US08178418B1 Method for fabricating intra-device isolation structure 有权
标题翻译：制造器件间隔离结构的方法
公开(公告)号：US08178418B1
公开(公告)日：2012-05-15
申请号：US13093726
申请日：2011-04-25
申请人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/3086
摘要： A method for fabricating intra-device isolation structure is provided, including providing a semiconductor substrate with a mask layer formed thereover. A plurality of first trenches is formed in the semiconductor substrate and the mask layer. A first insulating layer is formed in the first trenches. The mask layer is partially removed to expose a portion of the first insulating layer in the first trenches. A protection spacer is formed on a sidewall surface of the portion of the first insulating layer exposed by the mask layer to partially expose a portion of the mask layer between the first insulating layer. An etching process is performed to the mask layer exposed by the protection spacer and the semiconductor substrate thereunder, and a plurality of second trenches is formed in the semiconductor substrate and the mask layer. A second insulating layer is formed in the second trenches. The protection spacer, the mask layer, the first insulating layer and the second insulating layer over a top surface of the semiconductor substrate are then removed.
摘要翻译：提供一种用于制造器件间隔离结构的方法，包括提供其上形成有掩模层的半导体衬底。在半导体衬底和掩模层中形成多个第一沟槽。在第一沟槽中形成第一绝缘层。部分去除掩模层以暴露第一沟槽中的第一绝缘层的一部分。在由掩模层暴露的第一绝缘层的部分的侧壁表面上形成保护间隔物，以部分地暴露第一绝缘层之间的掩模层的一部分。对由保护间隔物和其下的半导体衬底暴露的掩模层进行蚀刻处理，并且在半导体衬底和掩模层中形成多个第二沟槽。在第二沟槽中形成第二绝缘层。然后去除半导体衬底的顶表面上的保护间隔物，掩模层，第一绝缘层和第二绝缘层。

60. 发明授权

US06727159B2 Method of forming a shallow trench isolation in a semiconductor substrate 有权
标题翻译：在半导体衬底中形成浅沟槽隔离的方法
公开(公告)号：US06727159B2
公开(公告)日：2004-04-27
申请号：US10163239
申请日：2002-06-04
申请人： Yi-Nan Chen , Hsien-Wen Liu , Kaan-Lu Tzou
发明人： Yi-Nan Chen , Hsien-Wen Liu , Kaan-Lu Tzou
IPC分类号： H01L2176
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/31612 , H01L21/76224
摘要： A method of forming a shallow trench isolation in a semiconductor substrate. First, a hard mask consisting of a pad nitride and a pad oxide is formed on the semiconductor substrate. The semiconductor substrate is anisotrpically etched to form a trench while the hard mask is used as the etching mask. A thermal oxide film is grown on the trench. Then, a nitride liner is formed on the thermal oxide film. Next, a silicon rich oxide layer is conformally deposited on the nitride liner by high density plasma chemical vapor deposition without a bias voltage applied to the semiconductor substrate. Then, a silicon oxide is deposited to fill the trench by high density plasma chemical vapor deposition while a bias voltage is applied to the semiconductor substrate.
摘要翻译：一种在半导体衬底中形成浅沟槽隔离的方法。首先，在半导体基板上形成由衬垫氮化物和衬垫氧化物构成的硬掩模。在使用硬掩模作为蚀刻掩模的情况下，各向异性蚀刻半导体衬底以形成沟槽。在沟槽上生长热氧化膜。然后，在热氧化膜上形成氮化物衬垫。接下来，通过高密度等离子体化学气相沉积在氮化物衬垫上共形沉积富硅氧化物层，而不施加施加到半导体衬底的偏置电压。然后，沉积氧化硅以通过高密度等离子体化学气相沉积来填充沟槽，同时向半导体衬底施加偏置电压。

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