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51. 发明授权

US08384125B2 Structure and method for a silicon controlled rectifier (SCR) structure for SOI technology 有权
标题翻译：用于SOI技术的可控硅整流器（SCR）结构的结构和方法
公开(公告)号：US08384125B2
公开(公告)日：2013-02-26
申请号：US13035549
申请日：2011-02-25
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
IPC分类号： H01L29/66
CPC分类号： H01L29/7436 , H01L27/0259 , H01L29/861
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

52. 发明授权

US07943438B2 Structure and method for a silicon controlled rectifier (SCR) structure for SOI technology 有权
标题翻译：用于SOI技术的可控硅整流器（SCR）结构的结构和方法
公开(公告)号：US07943438B2
公开(公告)日：2011-05-17
申请号：US12031084
申请日：2008-02-14
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
IPC分类号： H01L21/332
CPC分类号： H01L29/7436 , H01L27/0259 , H01L29/861
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

53. 发明授权

US08514535B2 Electrostatic discharge device control and structure 失效
标题翻译：静电放电装置的控制和结构
公开(公告)号：US08514535B2
公开(公告)日：2013-08-20
申请号：US12987276
申请日：2011-01-10
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
IPC分类号： H02H3/22
CPC分类号： H01L27/0285
摘要： Structures and methods for electrostatic discharge (ESD) device control in an integrated circuit are provided. An ESD protection structure includes an input/output (I/O) pad, and an ESD field effect transistor (FET) including a drain connected to the I/O pad, a source connected to ground, and a gate. A first control FET includes a drain connected to the I/O pad, a source connected to the gate of the ESD FET, and a gate connected to ground. A second control FET includes a drain connected to the gate of the ESD FET and the source of the first control FET, a source connected to ground, and a gate connected to the I/O pad.
摘要翻译：提供集成电路中静电放电（ESD）器件控制的结构和方法。 ESD保护结构包括输入/输出（I / O）焊盘和包括连接到I / O焊盘的漏极，连接到地的源极和栅极的ESD场效应晶体管（FET）。第一控制FET包括连接到I / O焊盘的漏极，连接到ESD FET的栅极的源极和连接到地的栅极。第二控制FET包括连接到ESD FET的栅极和第一控制FET的源极的漏极，连接到地的源极和连接到I / O焊盘的栅极。

54. 发明申请

US20120119257A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20120119257A1
公开(公告)日：2012-05-17
申请号：US13361051
申请日：2012-01-30
申请人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L29/73
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

55. 发明授权

US07399665B2 Electrostatic discharge protection device and method of fabricating same 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US07399665B2
公开(公告)日：2008-07-15
申请号：US11781370
申请日：2007-07-23
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

56. 发明申请

US20070285853A1 RC-Triggered Power Clamp Suppressing Negative Mode Electrostatic Discharge Stress 失效
标题翻译： RC触发电源钳位抑制负模式静电放电应力
公开(公告)号：US20070285853A1
公开(公告)日：2007-12-13
申请号：US11422608
申请日：2006-06-07
申请人： Robert J. Gauthier , Dimitrios K. Kontos , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Robert J. Gauthier , Dimitrios K. Kontos , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.
摘要翻译：一种静电放电（ESD）功率钳位电路，其包括耦合到多个串联反相器元件的RC延迟元件，其具有耦合到所述多个逆变器的功率钳位元件和ESD触发的保持器装置。在负模式ESD事件期间，ESD触发的保护装置被激活，并且帮助电源钳位元件上拉并强烈地传导电流以保护电路。另外，提供了电路中ESD保护的方法。该方法包括将RC延迟元件耦合到多个串联反相器元件的输入端，将多个串联反相器的输出与ESD触发的保持器装置和功率钳位元件耦合，将ESD触发的保持器装置触发在ESD ESD事件期间接通电源，并通过ESD触发的保护装置的辅助，通过电源钳位元件传导电流，以保护电路由于负ESD事件。

57. 发明授权

US07968908B2 Bidirectional electrostatic discharge protection structure for high voltage applications 有权
标题翻译：双向静电放电保护结构，适用于高压应用
公开(公告)号：US07968908B2
公开(公告)日：2011-06-28
申请号：US12563610
申请日：2009-09-21
申请人： Michel J. Abou-Khalil , Robert Gauthier , Junjun Li
发明人： Michel J. Abou-Khalil , Robert Gauthier , Junjun Li
IPC分类号： H01L29/73
CPC分类号： H01L23/60 , H01L27/0262 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Semiconductor structures providing protection against electrostatic events of both polarities are provided. A pair of p-n junctions is provided underneath a shallow trench isolation portion between a first-conductivity-type well and each of a signal-side second-conductivity-type well and an electrical-ground-side second-conductivity-type well in a semiconductor substrate. A second-conductivity-type doped region and a first-conductivity-type doped region are formed above each second-conductivity-type well such that a portion of the second-conductivity-type well resistively separates the second-conductivity-type doped region and the first-conductivity-type doped region within the semiconductor substrate. Each of the second-conductivity-type doped regions is wired either to a signal node or electrical ground. One of the two npn transistors and one of the two p-n diodes, each inherently present in the semiconductor structure, turn on to provide protection against electrical discharge events involving either type of excessive electrical charges.
摘要翻译：提供了提供两极性静电事件保护的半导体结构。在第一导电型阱与信号侧第二导电型阱和电 - 接地侧第二导电型阱中的每一个之间的浅沟槽隔离部分的半导体中设置一对pn结基质。第二导电型掺杂区域和第一导电型掺杂区域形成在每个第二导电型阱之上，使得第二导电型阱的一部分阱电阻地分离第二导电型掺杂区域，以及半导体衬底内的第一导电型掺杂区域。每个第二导电类型的掺杂区域被连接到信号节点或电接地。两个npn晶体管中的一个和两个固有地存在于半导体结构中的两个p-n二极管中的一个导通以提供防止涉及任何一种过量电荷的放电事件的保护。

58. 发明申请

US20110068364A1 BIDIRECTIONAL ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS 有权
标题翻译：用于高压应用的双向静电放电保护结构
公开(公告)号：US20110068364A1
公开(公告)日：2011-03-24
申请号：US12563610
申请日：2009-09-21
申请人： Michel J. Abou-Khalil , Robert Gauthier , Junjun Li
发明人： Michel J. Abou-Khalil , Robert Gauthier , Junjun Li
IPC分类号： H01L23/60
CPC分类号： H01L23/60 , H01L27/0262 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Semiconductor structures providing protection against electrostatic events of both polarities are provided. A pair of p-n junctions is provided underneath a shallow trench isolation portion between a first-conductivity-type well and each of a signal-side second-conductivity-type well and an electrical-ground-side second-conductivity-type well in a semiconductor substrate. A second-conductivity-type doped region and a first-conductivity-type doped region are formed above each second-conductivity-type well such that a portion of the second-conductivity-type well resistively separates the second-conductivity-type doped region and the first-conductivity-type doped region within the semiconductor substrate. Each of the second-conductivity-type doped regions is wired either to a signal node or electrical ground. One of the two npn transistors and one of the two p-n diodes, each inherently present in the semiconductor structure, turn on to provide protection against electrical discharge events involving either type of excessive electrical charges.
摘要翻译：提供了提供两极性静电事件保护的半导体结构。在第一导电型阱与信号侧第二导电型阱和电 - 接地侧第二导电型阱中的每一个之间的浅沟槽隔离部分的半导体中设置一对pn结基质。第二导电型掺杂区域和第一导电型掺杂区域形成在每个第二导电型阱之上，使得第二导电型阱的一部分阱电阻地分离第二导电型掺杂区域和半导体衬底内的第一导电型掺杂区域。每个第二导电类型的掺杂区域被连接到信号节点或电接地。两个npn晶体管中的一个和两个固有地存在于半导体结构中的两个p-n二极管中的一个导通以提供防止涉及任何一种过量电荷的放电事件的保护。

59. 发明申请

US20080145993A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20080145993A1
公开(公告)日：2008-06-19
申请号：US12036319
申请日：2008-02-25
申请人： Robert J. Gauthier , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L21/8228
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

60. 发明申请

US20080050880A1 STRUCTURE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE 审中-公开
标题翻译：具有可调触发电压的多器件半导体器件均匀触发的结构
公开(公告)号：US20080050880A1
公开(公告)日：2008-02-28
申请号：US11931634
申请日：2007-10-31
申请人： Michel Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher Putnam
发明人： Michel Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher Putnam
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/41733 , H01L29/41775 , H01L29/458 , H01L29/6653 , H01L29/7833 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.
摘要翻译：本发明提供了一种方法，其中提供了与扩展离子注入工艺无关的MOS沟道和硅化源极/漏极区之间的低电阻连接以及器件重叠电容。本发明的方法广泛地包括选择性地去除MOS结构的外部间隔物，然后在先前由外部间隔物保护的半导体衬底的暴露部分上选择性地镀覆金属或金属间化合物。本发明还提供了利用该方法形成的半导体结构。半导体结构包括硅化源/漏区和沟道区之间的低电阻连接，其包括选择性镀金属或金属间化合物。

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