专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US07765337B2 Direct memory access transfer completion notification 失效
标题翻译：直接内存访问传输完成通知
公开(公告)号：US07765337B2
公开(公告)日：2010-07-27
申请号：US11758167
申请日：2007-06-05
申请人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28 , G06F3/00 , G06F13/00
CPC分类号： G06F13/28
摘要： Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.
摘要翻译：提供方法，计算节点和计算机程序产品用于直接内存访问（“DMA”）传输完成通知。实施例包括通过原始计算节点上的原始DMA引擎确定要发送到目标计算节点的应用消息的数据描述符当前是否处于先进先出先入先出（FIFO）缓冲器依赖于先前与数据描述符相关联的序列号，当前在注入FIFO缓冲器中的描述符的总数以及存储在注入FIFO缓冲器中的最新数据描述符的当前序列号; 并且如果消息的数据描述符当前不在注入FIFO缓冲器中，则通知源DMA引擎上的处理器核心消息已被发送。

52. 发明授权

US06895416B2 Checkpointing filesystem 失效
标题翻译：检查点文件系统
公开(公告)号：US06895416B2
公开(公告)日：2005-05-17
申请号：US10258515
申请日：2002-02-25
申请人： Alan G. Gara , Mark E. Giampapa , Burkhard D. Steinmacher-Burow
发明人： Alan G. Gara , Mark E. Giampapa , Burkhard D. Steinmacher-Burow
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F11/1438 , Y10S707/99953 , Y10S707/99955
摘要： The present in invention is directed to a checkpointing filesystem of a distributed-memory parallel supercomputer comprising a node that accesses user data on the filesystem, the filesystem comprising an interface that is associated with a disk for storing the user data. The checkpointing filesystem provides for taking and checkpoint of the filesystem and rolling back to a previously taken checkpoint, as well as for writing user data to and deleting user data from the checkpointing filesystem. The checkpointing filesystem provides a recently written file allocation table (WFAT) for maintaining information regarding the user data written since a previously taken checkpoint and a recently deleted file allocation table (DFAT) for maintaining information regarding user data deleted from since the previously taken checkpoint, both of which are utilized by the checkpointing filesystem to take a checkpoint of the filesystem and rollback the filesystem to a previously taken checkpoint, as well as to write and delete user data from the checkpointing filesystem.
摘要翻译：本发明涉及一种分布式存储器并行超级计算机的检查点文件系统，其包括访问文件系统上的用户数据的节点，该文件系统包括与用于存储用户数据的盘相关联的接口。检查点文件系统提供文件系统的获取和检查点，并回滚到先前执行的检查点，以及从检查点文件系统向用户数据写入和删除用户数据。检查点文件系统提供最近写入的文件分配表（WFAT），用于维护关于自先前检查点以来写入的用户数据的信息，以及用于维护关于从先前检查点以来删除的用户数据的信息的最近删除的文件分配表（DFAT）这两个都由检查点文件系统用于采取文件系统的检查点并将文件系统回滚到先前执行的检查点，以及从检查点文件系统写入和删除用户数据。

53. 发明授权

US08103910B2 Local rollback for fault-tolerance in parallel computing systems 有权
标题翻译：并行计算系统容错的局部回滚
公开(公告)号：US08103910B2
公开(公告)日：2012-01-24
申请号：US12696780
申请日：2010-01-29
申请人： Matthias A. Blumrich , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Burkhard Steinmacher-Burow , Krishnan Sugavanam
发明人： Matthias A. Blumrich , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Burkhard Steinmacher-Burow , Krishnan Sugavanam
IPC分类号： G06F11/00
CPC分类号： G06F15/17381 , G06F9/30072
摘要： A control logic device performs a local rollback in a parallel super computing system. The super computing system includes at least one cache memory device. The control logic device determines a local rollback interval. The control logic device runs at least one instruction in the local rollback interval. The control logic device evaluates whether an unrecoverable condition occurs while running the at least one instruction during the local rollback interval. The control logic device checks whether an error occurs during the local rollback. The control logic device restarts the local rollback interval if the error occurs and the unrecoverable condition does not occur during the local rollback interval.
摘要翻译：控制逻辑设备在并行超级计算系统中执行本地回滚。超级计算系统包括至少一个高速缓冲存储器设备。控制逻辑设备确定本地回滚间隔。控制逻辑器件在本地回滚间隔中运行至少一条指令。控制逻辑设备评估在本地回滚间隔期间运行至少一条指令时是否发生不可恢复的条件。控制逻辑器件检查本地回滚期间是否发生错误。如果发生错误，并且在本地回滚间隔期间不发生不可恢复的条件，则控制逻辑设备将重新启动本地回滚间隔。

54. 发明申请

US20110119526A1 LOCAL ROLLBACK FOR FAULT-TOLERANCE IN PARALLEL COMPUTING SYSTEMS 有权
标题翻译：用于并行计算系统故障的局部回滚
公开(公告)号：US20110119526A1
公开(公告)日：2011-05-19
申请号：US12696780
申请日：2010-01-29
申请人： Matthias A. Blumrich , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Burkhard Steinmacher-Burow , Krishnan Sugavanam
发明人： Matthias A. Blumrich , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Burkhard Steinmacher-Burow , Krishnan Sugavanam
IPC分类号： G06F11/14 , H03M13/05 , G06F11/10
CPC分类号： G06F15/17381 , G06F9/30072
摘要： A control logic device performs a local rollback in a parallel super computing system. The super computing system includes at least one cache memory device. The control logic device determines a local rollback interval. The control logic device runs at least one instruction in the local rollback interval. The control logic device evaluates whether an unrecoverable condition occurs while running the at least one instruction during the local rollback interval. The control logic device checks whether an error occurs during the local rollback. The control logic device restarts the local rollback interval if the error occurs and the unrecoverable condition does not occur during the local rollback interval.
摘要翻译：控制逻辑设备在并行超级计算系统中执行本地回滚。超级计算系统包括至少一个高速缓冲存储器设备。控制逻辑设备确定本地回滚间隔。控制逻辑器件在本地回滚间隔中运行至少一条指令。控制逻辑设备评估在本地回滚间隔期间运行至少一条指令时是否发生不可恢复的条件。控制逻辑器件检查本地回滚期间是否发生错误。如果发生错误，并且在本地回滚间隔期间不发生不可恢复的条件，则控制逻辑设备将重新启动本地回滚间隔。

55. 发明申请

US20090006296A1 DMA ENGINE FOR REPEATING COMMUNICATION PATTERNS 失效
标题翻译： DMA引擎重复通信模式
公开(公告)号：US20090006296A1
公开(公告)日：2009-01-01
申请号：US11768795
申请日：2007-06-26
申请人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F15/18
CPC分类号： G06F15/163
摘要： A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.
摘要翻译：并行计算机系统被构造为互连的计算节点的网络，以操作用于在整个网络上执行通信的全局消息传递应用。每个计算节点包括具有存储器的一个或多个单独处理器，该存储器运行在每个计算节点处操作的全局消息传递应用的本地实例，以独立于在其他计算节点执行的处理操作来执行本地处理操作。每个计算节点还包括构造成通过描述多个注入FIFO的注入FIFO元数据与应用交互的DMA引擎，其中每个注入FIFO可以包含任意数量的消息描述符，以便处理具有固定处理开销的消息，而不管消息的数量描述符包含在注入FIFO中。

56. 发明授权

US07802025B2 DMA engine for repeating communication patterns 失效
标题翻译：用于重复通信模式的DMA引擎
公开(公告)号：US07802025B2
公开(公告)日：2010-09-21
申请号：US11768795
申请日：2007-06-26
申请人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F15/163
摘要： A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.
摘要翻译：并行计算机系统被构造为互连的计算节点的网络，以操作用于在整个网络上执行通信的全局消息传递应用。每个计算节点包括具有存储器的一个或多个单独处理器，该存储器运行在每个计算节点处操作的全局消息传递应用的本地实例，以独立于在其他计算节点执行的处理操作来执行本地处理操作。每个计算节点还包括构造成通过描述多个注入FIFO的注入FIFO元数据与应用交互的DMA引擎，其中每个注入FIFO可以包含任意数量的消息描述符，以便处理具有固定处理开销的消息，而不管消息的数量描述符包含在注入FIFO中。

57. 发明授权

US07617366B2 Method and apparatus for filtering snoop requests using mulitiple snoop caches 失效
标题翻译：使用多播监听高速缓存来过滤窥探请求的方法和装置
公开(公告)号：US07617366B2
公开(公告)日：2009-11-10
申请号：US12113756
申请日：2008-05-01
申请人： Matthias A. Blumrich , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht , Valentina Salapura
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0831
摘要： A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associative cache is considered to have wrapped when all of the sets within the cache have been replaced. The starting point for cache wrap detection is the state of the cache sets at the time of the previous cache wrap. The method and apparatus is preferably implemented in a snoop filter having filter mechanisms that rely upon detecting the cache wrap condition. These snoop filter mechanisms requiring this information are operatively coupled with cache wrap detection logic adapted to detect the cache wrap event, and perform an indication step to the snoop filter mechanisms. In the various embodiments, cache wrap detection logic is implemented using registers and comparators, loadable counters, or a scoreboard data structure.
摘要翻译：一种用于在具有处理器和高速缓存的计算环境中检测高速缓存包装条件的方法和装置。当高速缓存的全部内容相对于特定的启动状态被替换时，检测到缓存包装条件。当缓存中的所有集合已被替换时，集合关联缓存被认为已被包装。高速缓存包检测的起始点是先前高速缓存包装时高速缓存集的状态。该方法和装置优选地在具有依赖于检测高速缓存包装条件的过滤机构的窥探过滤器中实现。这些需要该信息的窥探过滤机构可操作地与适用于检测高速缓存包裹事件的高速缓存包检测逻辑耦合，并且向窥探过滤机构执行指示步骤。在各种实施例中，使用寄存器和比较器，可加载计数器或记分板数据结构来实现高速缓存封包检测逻辑。

58. 发明申请

US20080209128A1 METHOD AND APPARATUS FOR DETECTING A CACHE WRAP CONDITION 失效
标题翻译：用于检测高速缓存条件的方法和装置
公开(公告)号：US20080209128A1
公开(公告)日：2008-08-28
申请号：US12113756
申请日：2008-05-01
申请人： Matthias A. Blumrich , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht , Valentina Salapura
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831
摘要： A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associative cache is considered to have wrapped when all of the sets within the cache have been replaced. The starting point for cache wrap detection is the state of the cache sets at the time of the previous cache wrap. The method and apparatus is preferably implemented in a snoop filter having filter mechanisms that rely upon detecting the cache wrap condition. These snoop filter mechanisms requiring this information are operatively coupled with cache wrap detection logic adapted to detect the cache wrap event, and perform an indication step to the snoop filter mechanisms. In the various embodiments, cache wrap detection logic is implemented using registers and comparators, loadable counters, or a scoreboard data structure.
摘要翻译：一种用于在具有处理器和高速缓存的计算环境中检测高速缓存包装条件的方法和装置。当高速缓存的全部内容相对于特定的启动状态被替换时，检测到缓存包装条件。当缓存中的所有集合已被替换时，集合关联缓存被认为已被包装。高速缓存包检测的起始点是先前高速缓存包装时高速缓存集的状态。该方法和装置优选地在具有依赖于检测高速缓存包装条件的过滤机构的窥探过滤器中实现。这些需要该信息的窥探过滤机构可操作地与适用于检测高速缓存包裹事件的高速缓存包检测逻辑耦合，并且向窥探过滤机构执行指示步骤。在各种实施例中，使用寄存器和比较器，可加载计数器或记分板数据结构来实现高速缓存封包检测逻辑。

59. 发明授权

US07386684B2 Method and apparatus for detecting a cache wrap condition 有权
标题翻译：用于检测缓存包装条件的方法和装置
公开(公告)号：US07386684B2
公开(公告)日：2008-06-10
申请号：US11093132
申请日：2005-03-29
申请人： Matthias A. Blumrich , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht , Valentina Salapura
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0831
摘要： A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associative cache is considered to have wrapped when all of the sets within the cache have been replaced. The starting point for cache wrap detection is the state of the cache sets at the time of the previous cache wrap. The method and apparatus is preferably implemented in a snoop filter having filter mechanisms that rely upon detecting the cache wrap condition. These snoop filter mechanisms requiring this information are operatively coupled with cache wrap detection logic adapted to detect the cache wrap event, and perform an indication step to the snoop filter mechanisms. In the various embodiments, cache wrap detection logic is implemented using registers and comparators, loadable counters, or a scoreboard data structure.
摘要翻译：一种用于在具有处理器和高速缓存的计算环境中检测高速缓存包装条件的方法和装置。当高速缓存的全部内容相对于特定的启动状态被替换时，检测到缓存包装条件。当缓存中的所有集合已被替换时，集合关联缓存被认为已被包装。高速缓存包检测的起始点是先前高速缓存包装时高速缓存集的状态。该方法和装置优选地在具有依赖于检测高速缓存包装条件的过滤机构的窥探过滤器中实现。这些需要该信息的窥探过滤机构可操作地与适用于检测高速缓存包裹事件的高速缓存包检测逻辑耦合，并且向窥探过滤机构执行指示步骤。在各种实施例中，使用寄存器和比较器，可加载计数器或记分板数据结构来实现高速缓存封包检测逻辑。

60. 发明申请

US20090006873A1 POWER THROTTLING OF COLLECTIONS OF COMPUTING ELEMENTS 失效
标题翻译：计算元素收集的功率曲线
公开(公告)号：US20090006873A1
公开(公告)日：2009-01-01
申请号：US11768752
申请日：2007-06-26
申请人： Ralph E. Bellofatto , Paul W. Coteus , Paul G. Crumley , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf Haring , Mark G. Megerian , Martin Ohmacht , Don D. Reed , Richard A. Swetz , Todd Takken
发明人： Ralph E. Bellofatto , Paul W. Coteus , Paul G. Crumley , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf Haring , Mark G. Megerian , Martin Ohmacht , Don D. Reed , Richard A. Swetz , Todd Takken
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/206
摘要： An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.
摘要翻译：用于控制计算机中的电力使用的装置和方法包括与本地控制装置通信的多个计算机，以及向本地控制装置和计算机供电的电源。多个传感器与计算机通信以确定计算机的功率使用，并且系统控制装置与计算机通信以控制计算机的电力使用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式