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51. 发明授权

US06259142B1 Multiple split gate semiconductor device and fabrication method 失效
标题翻译：多分裂栅极半导体器件及其制造方法
公开(公告)号：US06259142B1
公开(公告)日：2001-07-10
申请号：US09056837
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2976
CPC分类号： H01L29/66484 , H01L29/7831
摘要： A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.
摘要翻译：具有多个分割栅极的半导体集成电路使用第一多晶硅层和第二多晶硅层形成，以在有源区内形成交替的第一和第二栅电极。交替的栅电极通过与每个第一栅电极的侧壁相邻形成的栅极绝缘层彼此电隔离。源极和漏极区域形成在多分裂栅极的端部附近以限定沟道区域。

52. 发明授权

US06201278B1 Trench transistor with insulative spacers 失效
标题翻译：带绝缘垫片的沟槽晶体管
公开(公告)号：US06201278B1
公开(公告)日：2001-03-13
申请号：US09028896
申请日：1998-02-24
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31062
CPC分类号： H01L29/7834 , H01L29/66621
摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要翻译：公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与栅电极。有利地，沟道长度明显小于沟槽长度。

53. 发明授权

US6127719A Subfield conductive layer and method of manufacture 失效
标题翻译：子场导电层及其制造方法
公开(公告)号：US6127719A
公开(公告)日：2000-10-03
申请号：US038464
申请日：1998-03-11
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/74 , H01L29/00 , H01L31/119
CPC分类号： H01L21/74
摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.
摘要翻译：提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。在形成场电介质之后，将子场导电层置于硅衬底内。导电层表示驻留在隔离器件之间的掩埋互连。然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。

54. 发明授权

US6100146A Method of forming trench transistor with insulative spacers 失效
标题翻译：用绝缘间隔物形成沟槽晶体管的方法
公开(公告)号：US6100146A
公开(公告)日：2000-08-08
申请号：US739595
申请日：1996-10-30
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7834 , H01L29/66621
摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要翻译：公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与栅电极。有利地，沟道长度明显小于沟槽长度。

55. 发明授权

US06080629A Ion implantation into a gate electrode layer using an implant profile displacement layer 失效
标题翻译：使用植入物轮廓位移层将离子注入到栅极电极层中
公开(公告)号：US06080629A
公开(公告)日：2000-06-27
申请号：US837579
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/28035
摘要： A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.
摘要翻译：将掺杂剂注入到薄栅电极层中的方法包括在栅电极层上形成位移层以形成组合位移/栅极电极层，并将掺杂剂注入到组合层中。注入的掺杂剂分布基本上完全位于栅极电极层内，或者基本上部分地位于栅极电极层内部分地位于位移层内。如果位移层最终被去除，则注入的掺杂剂的至少一部分保留在栅电极层内。栅极电极层可以在图案化之前或之后被注入，并蚀刻栅电极层以限定栅电极。此外，可以使用两种不同的选择性植入来限定不同掺杂剂浓度的分开的区域，例如P型多晶硅和N型多晶硅区域。每个区域可以利用单独的位移层厚度，这允许不同原子质量的掺杂剂使用类似的注入能量。可以使用较高的注入能量来掺杂比正常范围统计要求更薄的栅极电极层，而不会使植入物渗入下面的结构。

56. 发明授权

US6048785A Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching 失效
标题翻译：半导体制造方法，其使用片段拼接来组合由标线片图像定义的多个场
公开(公告)号：US6048785A
公开(公告)日：2000-04-11
申请号：US876628
申请日：1997-06-16
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895 , Y10S438/946 , Y10S438/949
摘要： Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnected by imaging using a stitching reticle having an exposure field overlapping a plurality of the regions. The combination of reticle-imaged fields effectively increases the size of a field formed using a step and repeat technique while achieving high imaging resolution within the combined regions. Similarly, a plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are interconnected using a stitch mask and etch operation that combines the regions.
摘要翻译：在半导体衬底上的多个区域的每个区域以由掩模版定义的曝光区域成像。这些区域通过诸如场氧化物或沟槽隔离的隔离在半导体衬底内分离和电隔离。这些区域通过使用具有与多个区域重叠的曝光场的拼接掩模版进行成像来互连。掩模版成像场的组合有效地增加了使用步骤和重复技术形成的场的大小，同时在组合区域内实现高成像分辨率。类似地，使用多个集成芯片组中的每一个的单独掩模版成像，在单个半导体晶片上构造包括微处理器，存储器和支持芯片的多个集成芯片组。使用组合这些区域的针迹掩模和蚀刻操作来使不同的电路互连。

57. 发明授权

US6043544A Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric 有权
标题翻译：具有基本上均匀的掺杂分布的半导体栅极导体对掺杂剂渗透到下面的栅极电介质中具有最小的敏感性
公开(公告)号：US6043544A
公开(公告)日：2000-03-28
申请号：US140202
申请日：1998-08-26
申请人： Mark W. Michael , Robert Dawson
发明人： Mark W. Michael , Robert Dawson
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/76
CPC分类号： H01L21/28035 , H01L21/823842
摘要： A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioning is achieved by using separate implants of different energies depending upon whether the gate conductor connotes a PMOS or NMOS transistor. A layer of polysilicon used to form the gate conductor is doped before patterning so that the source and drain regions are protected. A low energy implant is performed when implanting a fast diffuser such as boron, and a high energy implant is performed when implanting a slow diffuser like arsenic. This enables optimum positioning of the impurities throughout the gate conductor cross-section after heat cycles are applied. Fast diffusers are initially placed far from the bottom surface of the polysilicon, and diffuse near the bottom surface of the polysilicon when heat is applied. Slow diffusers are initially placed closer to the bottom surface of the polysilicon, since they do not diffuse as readily. The source and drain regions are implanted using a very low energy implant, separately from the polysilicon implants, to produce a desirable shallow source and drain region within the semiconductor substrate.
摘要翻译：提出了一种半导体制造工艺，其优化栅极导体内杂质的位置，栅极导体中跨越栅极导体的源极/漏极。通过使用不同能量的单独注入来取决于栅极导体是指PMOS还是NMOS晶体管来实现最佳定位。用于形成栅极导体的多晶硅层在图案化之前被掺杂，使得源极和漏极区域受到保护。当植入诸如硼的快速扩散器时执行低能量注入，并且当植入像砷这样的慢扩散器时执行高能量注入。这使得在施加热循环之后，杂质在整个栅极导体横截面中的最佳定位。最初放置快速扩散器远离多晶硅的底表面，并在加热时在多晶硅的底表面附近扩散。缓慢扩散器最初放置得更靠近多晶硅的底表面，因为它们不会容易地扩散。使用与多晶硅植入物分开的非常低能量的注入来注入源极区和漏极区，以在半导体衬底内产生期望的浅源极和漏极区。

58. 发明授权

US5968843A Method of planarizing a semiconductor topography using multiple polish pads 失效
标题翻译：使用多个抛光垫平面化半导体形貌的方法
公开(公告)号：US5968843A
公开(公告)日：1999-10-19
申请号：US768278
申请日：1996-12-18
申请人： Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/302
CPC分类号： H01L21/31053
摘要： An improved method for planarizing an interlevel dielectric comprising two chemical mechanical polish steps. After an interlevel dielectric containing a topographical valley between a pair of topographical peaks is formed, the dielectric is chemically-mechanically polished in a first polish step at a first force using a first polish pad having a first rigidity to round the sharp dielectric corners or edges that exist at the transition between the peaks and valleys. After the first polish step has rounded the edges, a second polish step is performed with a second polish pad of second rigidity. The second polish pad is more rigid than the first polish pad and the second force is greater than the first. The second polish steps uses a high viscosity slurry to reduce slurry turnover in the regions proximate to the dielectric valleys thereby reducing the chemical etching in the valleys and improving the planarization efficiency.
摘要翻译：一种用于平坦化层间电介质的改进方法，包括两个化学机械抛光步骤。在形成包含一对形貌峰之间的形貌谷的层间电介质之后，使用具有第一刚性的第一抛光垫在第一抛光步骤中以第一力进行化学机械抛光的电介质以使尖锐的电介质拐角或边缘存在于峰谷之间的过渡处。在第一抛光步骤使边缘变圆之后，用第二刚性的第二抛光垫进行第二抛光步骤。第二抛光垫比第一抛光垫更刚性，第二抛光垫大于第一抛光垫。第二抛光步骤使用高粘度浆料来减少靠近电介质谷的区域中的浆料周转，从而减少了谷中的化学蚀刻并提高了平坦化效率。

59. 发明授权

US5963803A Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths 失效
标题翻译：制造具有不同栅极厚度和间隔宽度的N沟道和P沟道IGFET的方法
公开(公告)号：US5963803A
公开(公告)日：1999-10-05
申请号：US17254
申请日：1998-02-02
申请人： Robert Dawson , Mark W. Michael , Charles E. May
发明人： Robert Dawson , Mark W. Michael , Charles E. May
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/02
CPC分类号： H01L21/82385 , H01L21/823864 , H01L27/0922
摘要： A method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths is disclosed. The method includes providing a semiconductor substrate with a first active region of a first conductivity type and a second active region of a second conductivity type, forming a first gate over the first active region and a second gate over the second active region, wherein the second gate has a substantially greater thickness than the first gate, forming first spacers in close proximity to opposing sidewalls of the first gate and second spacers in close proximity to opposing sidewalls of the second gate, wherein the second spacers have a substantially greater width than the first spacers due to the second gate having a substantially greater thickness than the first gate, and forming a first source and a first drain of the second conductivity type in the first active region and a second source and a second drain of the first conductivity type in the second active region. Preferably, the N-channel device is formed in the first active region, the P-channel device is formed in the second active region, and the N-channel and P-channel devices include lightly and heavily doped source and drain regions. In this manner, the relatively thick gate for the P-channel device reduces boron penetration, and the relatively wide spacers for the P-channel device offset the rapid diffusion of boron in the heavily doped source and drain regions of the P-channel device during high temperature processing so that the lightly doped source and drain regions for the N-channel and P-channel devices have the desired sizes.
摘要翻译：公开了一种制造具有不同栅极厚度和间隔物宽度的N沟道和P沟道IGFET的方法。该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，其中第二有源区栅极具有比第一栅极大得多的厚度，在第二栅极的相对侧壁附近形成第一间隔物，其紧邻第一栅极的相对侧壁和第二间隔物，其中第二间隔物具有比第一栅极大得多的宽度由于第二栅极具有比第一栅极大得多的厚度的间隔物，以及在第一有源区中形成第二导电类型的第一源极和第一漏极，以及在第一有源区中形成第一导电类型的第二源极和第二漏极第二活跃区域。优选地，N沟道器件形成在第一有源区中，P沟道器件形成在第二有源区中，并且N沟道和P沟道器件包括轻掺杂和重掺杂的源极和漏极区。以这种方式，用于P沟道器件的相对较厚的栅极减少硼渗透，并且用于P沟道器件的相对较宽的间隔物抵消P沟道器件的重掺杂源极和漏极区域中硼的快速扩散，高温处理使得用于N沟道和P沟道器件的轻掺杂源极和漏极区域具有期望的尺寸。

60. 发明授权

US5937299A Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls 失效
标题翻译：用于形成具有硅化物源极/漏极接触的IGFET的方法，其紧邻具有倾斜侧壁的栅极
公开(公告)号：US5937299A
公开(公告)日：1999-08-10
申请号：US837522
申请日：1997-04-21
申请人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
发明人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/417 , H01L29/423
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/0847 , H01L29/41775 , H01L29/42376 , H01L29/66628 , H01L29/665
摘要： An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide. In this manner, a highly miniaturized IGFET can be provided with densely-packed gate, source and drain contacts without the need for sidewall spacers adjacent to the gate.
摘要翻译：公开了具有源极和漏极触点的IGFET，其紧邻具有倾斜侧壁的栅极。制造IGFET的方法包括在半导体衬底上形成栅极，其中栅极包括顶表面，底表面和相对的侧壁，并且顶表面具有比底表面大得多的长度，形成源极和漏极延伸到衬底中，在栅极，源极和漏极上沉积接触材料，以及在栅极上形成栅极接触，源极上的源极接触和漏极上的漏极接触。由于栅极侧壁的逆向斜坡，栅极与源极和漏极接触分离，并且由于接触材料中缺少台阶覆盖，栅极接触与源极和漏极接触分离。优选地，接触材料是难熔金属，并且通过将难熔金属转化为硅化物形成触点。以这种方式，高度小型化的IGFET可以设置有密集封装的栅极，源极和漏极接触，而不需要邻近栅极的侧壁间隔。

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