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51. 发明授权

US06803805B2 Distributed DC voltage generator for system on chip 失效
标题翻译：分布式直流电压发生器，用于片上系统
公开(公告)号：US06803805B2
公开(公告)日：2004-10-12
申请号：US10118753
申请日：2002-04-09
申请人： Li-Kong Wang , Louis L. Hsu , Fanchieh Yee
发明人： Li-Kong Wang , Louis L. Hsu , Fanchieh Yee
IPC分类号： G05F302
CPC分类号： G06F1/26 , Y10T307/25
摘要： A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.
摘要翻译：提供了一种芯片系统（SOC电压发生器）系统，用于向具有SOC设计的芯片上的多个单元提供至少一个电压电平。该系统包括分布在整个芯片上的多个本地直流电压发生器，每个局部直流电压发生器独立地向多个单元中的至少一个单元提供电压，每个局部直流电压发生器包括输出一个泵控制信号的调节器系统; 以及泵系统，接收所述一个泵控制信号，并根据所述一个泵控制信号输出至少一个电压电平。此外，提供了一种用于向具有SOC设计的芯片上的多个单元提供电压的方法。该方法包括在整个芯片上分配多个局部DC电压发生器的步骤; 并且经由所述多个本地DC电压发生器向所述多个单元提供至少一个电压电平。

52. 发明授权

US06728916B2 Hierarchical built-in self-test for system-on-chip design 有权
标题翻译：分层内置自检系统级芯片设计
公开(公告)号：US06728916B2
公开(公告)日：2004-04-27
申请号：US09863952
申请日：2001-05-23
申请人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
发明人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
IPC分类号： G01R3128
CPC分类号： G06F11/27
摘要： Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.
摘要翻译：分层内置的自检方法和安排，用于验证系统功能。因此，提供了一种有效的内置自检方法，用于进行完整的片上系统测试，以确保片上系统设计的电路可靠性和性能。作为一个额外的优势，系统级芯片应用程序的开发成本有所降低。

53. 发明授权

US06720595B2 Three-dimensional island pixel photo-sensor 有权
标题翻译：三维岛像素光电传感器
公开(公告)号：US06720595B2
公开(公告)日：2004-04-13
申请号：US09922077
申请日：2001-08-06
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L31062
CPC分类号： H01L27/14634 , H01L27/1463 , H01L27/14643
摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.
摘要翻译：公开了一种用于光电二极管阵列的方法和结构，该阵列包括多个光电二极管芯，沿芯的外部的感光侧壁，芯之上的逻辑电路，分离芯的沟槽和沟槽中的透明材料。利用本发明，侧壁垂直于接收入射光的光电二极管的表面。感光侧壁包括当用光照射时引起电子转移的结区域。侧壁包围围绕每个岛芯的四个垂直侧壁。逻辑电路阻挡来自芯的光，因此光仅主要由侧壁感测。

54. 发明授权

US06594196B2 Multi-port memory device and system for addressing the multi-port memory device 失效
公开(公告)号：US06594196B2
公开(公告)日：2003-07-15
申请号：US09725967
申请日：2000-11-29
申请人： Louis L Hsu , Tin-chee Lo , Li-Kong Wang
发明人： Louis L Hsu , Tin-chee Lo , Li-Kong Wang
IPC分类号： G11C800
CPC分类号： G06F13/18 , G11C7/1075 , G11C8/16 , G11C11/405
摘要： A multi-port memory array is associated with wordlines and bit-lines to perform data read/write operation and has multi-port memory cells each of which includes multiple ports through which the wordlines and bit-lines are provided, multiple transistor devices each of which corresponds to each of the multiple ports and is coupled to a wordline and a bit-line through a corresponding port, each transistor device being gated by a wordline and having a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated. A system for addressing the multi-port memory array includes a conflict detector for detecting a conflict between two or more of the row address signals to generate a conflict control signal corresponding to the conflict detected, a priority logic circuit for performing a logic operation with respect to the request command signals based on a predetermined priority logic to generate prioritized signals, and a selection unit for selecting one of a request command signal and a prioritized signal corresponding to the request command signal in response to the conflict control signal, where a signal selected by the selection unit selects a corresponding one of the row address signals.

55. 发明授权

US06556477B2 Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same 有权
标题翻译：具有SRAM，DRAM和闪速存储器的集成芯片及其制造方法
公开(公告)号：US06556477B2
公开(公告)日：2003-04-29
申请号：US09861788
申请日：2001-05-21
申请人： Louis L. Hsu , Carl Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl Radens , Li-Kong Wang
IPC分类号： G11C1134
CPC分类号： H01L27/105 , G11C11/005 , H01L27/1052
摘要： A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a deep trench DRAM device. A method is also presented for fabricating the memory system on one substrate having the SRAM device, the DRAM device and the Flash memory device.
摘要翻译：提出了在一个衬底上制造的半导体存储器系统，其包括SRAM器件，DRAM器件和闪存器件。在一个实施例中，SRAM器件是高电阻负载SRAM器件。在另一个实施例中，DRAM器件是深沟槽DRAM器件。还提出了一种用于在具有SRAM器件，DRAM器件和闪存器件的一个衬底上制造存储器系统的方法。

56. 发明授权

US06542973B2 Integrated redundancy architecture system for an embedded DRAM 有权
标题翻译：嵌入式DRAM的集成冗余架构系统
公开(公告)号：US06542973B2
公开(公告)日：2003-04-01
申请号：US09898434
申请日：2001-07-03
申请人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata , Gregory J. Fredeman
发明人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata , Gregory J. Fredeman
IPC分类号： G06F1200
CPC分类号： G11C29/846 , G06F12/0893
摘要： An integrated redundancy eDRAM architecture system for an embedded DRAM macro system having a wide data bandwidth and wide internal bus width is disclosed which provides column and row redundancy for defective columns and rows of the eDRAM macro system. Internally generated column and row addresses of defective columns and rows of each micro-cell block are stored in a memory device, such as a fuse bank, during an eDRAM macro test mode in order for the information to be quickly retrieved during each cycle of eDRAM operation to provide an SRAM-like operation. A column steering circuit steers column redundant elements to replace defective column elements. Redundancy information is either supplied from a SRAM fuse data storage device or from a TAG memory device depending on whether a read or write operation, respectively, is being performed. The integrated redundancy eDRAM architecture system enables data to be sent and received to and from the eDRAM macro system without adding any extra delay to the data flow, thereby protecting data flow pattern integrity.
摘要翻译：公开了一种用于具有宽数据带宽和宽内部总线宽度的嵌入式DRAM宏系统的集成冗余eDRAM架构系统，其为eDRAM宏系统的有缺陷的列和行提供列和行冗余。在eDRAM宏测试模式期间，每个微小区块的有缺陷的列和行的内部生成的列和行地址存储在诸如保险丝库的存储器件中，以便在eDRAM的每个周期期间快速检索信息操作提供类似SRAM的操作。列转向电路引导列冗余元件来替换有缺陷的列元素。根据是否正在执行读取或写入操作，冗余信息是从SRAM熔丝数据存储设备提供的，或者从TAG存储设备提供的。集成冗余eDRAM架构系统使数据能够从eDRAM宏系统发送和接收数据，而不会对数据流增加任何额外的延迟，从而保护数据流模式的完整性。

57. 发明授权

US06492227B1 Method for fabricating flash memory device using dual damascene process 失效
标题翻译：使用双镶嵌工艺制造闪存器件的方法
公开(公告)号：US06492227B1
公开(公告)日：2002-12-10
申请号：US09624563
申请日：2000-07-24
申请人： Li-Kong Wang , Louis L. Hsu , Wei Hwang
发明人： Li-Kong Wang , Louis L. Hsu , Wei Hwang
IPC分类号： H01L218234
CPC分类号： H01L21/28273
摘要： A method is provided for fabricating memory devices on a semiconductor substrate using a dual damascene process. The method includes the steps of forming at least one dummy gate structure for at least one memory device on the semiconductor substrate, depositing dielectric material on surroundings of the at least one dummy gate structure, etching the dielectric material and the at least one dummy gate structure to form at least one control gate void and at least one floating gate void, forming a gate dielectric layer on a bottom surface of the at least one floating gate void, depositing floating gate material on the gate dielectric layer in the at least one floating gate void to form a floating gate, depositing a dielectric layer on the floating gate, and depositing control gate material on the dielectric layer in the at least one control gate void to form a control gate. Support devices may be fabricated on the semiconductor substrate by a single damascene process this is integrated with the processes of fabricating the memory devices, so that top surfaces of the support devices and the memory devices are substantially coplanar.
摘要翻译：提供了一种使用双镶嵌工艺在半导体衬底上制造存储器件的方法。该方法包括以下步骤：在半导体衬底上形成用于至少一个存储器件的至少一个虚拟栅极结构，在至少一个虚拟栅极结构的周围沉积介电材料，蚀刻电介质材料和至少一个虚拟栅极结构以形成至少一个控制栅极空隙和至少一个浮置栅极空隙，在所述至少一个浮置栅极空隙的底表面上形成栅极电介质层，在至少一个浮置栅极中的栅极介电层上沉积浮置栅极材料空隙以形成浮置栅极，在浮置栅极上沉积介电层，以及将控制栅极材料沉积在所述至少一个控制栅极中的介电层上以形成控制栅极。可以通过单个镶嵌工艺在半导体衬底上制造支撑装置，其与制造存储器件的工艺集成，使得支撑装置和存储装置的顶表面基本上共面。

58. 发明授权

US06411157B1 Self-refresh on-chip voltage generator 失效
标题翻译：自刷新片上电压发生器
公开(公告)号：US06411157B1
公开(公告)日：2002-06-25
申请号：US09606650
申请日：2000-06-29
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： G05F302
CPC分类号： G11C11/4074 , G11C11/406 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , H02M3/073
摘要： A voltage control system and methodology for maintaining internally generated voltage levels in a semiconductor chip. The method comprises the steps of intermittently sampling an internal voltage supply level during a low power or “sleep” mode of operation; comparing the internal voltage supply level against a predetermined voltage reference level; and, activating a voltage supply generator for increasing the internal voltage supply level when the internal voltage supply level falls below the predetermined voltage reference level. The voltage supply generator is subsequently deactivated when the voltage supply level is restored to the predetermined voltage reference level. The sampling cycle may be appropriately tailored according to chip condition, chip temperature, and chip size. In one embodiment, the voltage control system and methodology is implemented in DRAM circuits during a refresh operation. The voltage levels that are suitable for sampling including DRAM band-gap reference voltage, boost wordline line voltage, wordline low voltage, bitline high voltage and bitline equalization voltages.
摘要翻译：一种用于维持半导体芯片内部产生的电压电平的电压控制系统和方法。该方法包括以下步骤：在低功率或“睡眠”操作模式期间间歇地采样内部电压供应电平; 将内部电压供应电平与预定电压参考电平进行比较; 以及当所述内部电压供应电平低于所述预定电压参考电平时激活用于增加所述内部电压供应电平的电压源发生器。当电压供应电平恢复到预定电压参考电平时，电压发生器随后被去激活。采样周期可以根据芯片条件，芯片温度和芯片尺寸进行适当调整。在一个实施例中，电压控制系统和方法在刷新操作期间在DRAM电路中实现。适用于采样的电压电平，包括DRAM带隙参考电压，升压字线电压，字线低电压，位线高电压和位线均衡电压。

59. 发明授权

US06358791B1 Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby 失效
标题翻译：用于在体硅和绝缘体上硅（SOI）晶片上增加非常大规模集成（VLSI）电容器尺寸的方法和由此形成的结构
公开(公告)号：US06358791B1
公开(公告)日：2002-03-19
申请号：US09325731
申请日：1999-06-04
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L218242
CPC分类号： H01L29/66181 , H01L27/0805 , H01L27/1203 , H01L28/90 , H01L29/945 , Y10S257/905 , Y10S438/947 , Y10S438/948
摘要： A method of forming a semiconductor device, includes forming at least one conductive island having a predetermined sidewall angle in a conductive substrate, forming a dielectric material over the at least one island, forming a conductive material over the dielectric material, and forming a contact to the conductive material and the at least one island.
摘要翻译：一种形成半导体器件的方法，包括在导电衬底中形成具有预定侧壁角的至少一个导电岛，在所述至少一个岛上形成电介质材料，在所述电介质材料上形成导电材料，并形成接触所述导电材料和所述至少一个岛。

60. 发明授权

US06337513B1 Chip packaging system and method using deposited diamond film 有权
公开(公告)号：US06337513B1
公开(公告)日：2002-01-08
申请号：US09449886
申请日：1999-11-30
申请人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsorng-Dih Yuan
发明人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsorng-Dih Yuan
IPC分类号： H01L2348
CPC分类号： H01L23/473 , H01L23/3677 , H01L23/3732 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/051 , H01L2224/05548 , H01L2224/0557 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01019 , H01L2924/10253 , Y10S257/93 , H01L2924/00 , H01L2224/05599
摘要： A chip packaging system and method for providing enhanced thermal cooling including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.

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