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51. 发明申请

US20070153616A1 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20070153616A1
公开(公告)日：2007-07-05
申请号：US11640956
申请日：2006-12-19
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.
摘要翻译：提供了相变存储器件。相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

52. 发明申请

US20060209616A1 Phase change memory device and associated wordline driving circuit 失效
公开(公告)号：US20060209616A1
公开(公告)日：2006-09-21
申请号：US11319604
申请日：2005-12-29
申请人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
发明人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
IPC分类号： G11C8/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028
摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.

53. 发明申请

US20090168493A1 SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL AND METHOD OF MANUFACTURING THE STACKED MEMORY CELL 有权
标题翻译：具有堆叠存储单元的半导体存储器件和制造堆叠存储器单元的方法
公开(公告)号：US20090168493A1
公开(公告)日：2009-07-02
申请号：US12273225
申请日：2008-11-18
申请人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
发明人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
IPC分类号： G11C11/00 , H01L21/00 , H01L47/00
CPC分类号： G11C13/003 , G11C5/02 , G11C7/18 , G11C11/15 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/71 , G11C2213/74 , G11C2213/79 , H01L27/24
摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

54. 发明授权

US07548446B2 Phase change memory device and associated wordline driving circuit 失效
标题翻译：相变存储器件和相关的字线驱动电路
公开(公告)号：US07548446B2
公开(公告)日：2009-06-16
申请号：US11319604
申请日：2005-12-29
申请人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
发明人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028
摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.
摘要翻译：半导体存储器件包括多个字线驱动电路，其适于响应于全局字线和地址信号的逻辑状态来控制子字线的电压电平。字线驱动电路包括第一和第二晶体管，其被配置为当全局字线和地址信号具有第一逻辑状态并且当全局字线或地址信号具有第一电压电平时，将子字线保持在第一电压电平第二逻辑状态。

55. 发明申请

US20080232177A1 NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20080232177A1
公开(公告)日：2008-09-25
申请号：US12052761
申请日：2008-03-21
申请人： Byung-gil Choi , Du-eung Kim
发明人： Byung-gil Choi , Du-eung Kim
IPC分类号： G11C7/00
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： Disclosed is a nonvolatile memory device using a variable resistive element, and a data read circuit for use in variable resistive memory devices. More specifically, embodiments of the invention provide a data read circuit with one or more decoupling units to remove noise from one or more corresponding control signals. For instance, embodiments of the invention remove noise from a clamping control signal, a read bias control signal, and/or precharge signal. The disclosed decoupling units may be used alone or in any combination. Embodiments of the invention are beneficial because they can increase sensing margin and improve the reliability of read operations in memory devices with variable resistive elements.
摘要翻译：公开了一种使用可变电阻元件的非易失性存储器件和用于可变电阻存储器件的数据读取电路。更具体地，本发明的实施例提供具有一个或多个去耦单元的数据读取电路，以从一个或多个相应的控制信号中去除噪声。例如，本发明的实施例从钳位控制信号，读取偏置控制信号和/或预充电信号中去除噪声。所公开的去耦单元可以单独使用或以任何组合使用。本发明的实施例是有益的，因为它们可以增加感测裕度并提高具有可变电阻元件的存储器件中的读取操作的可靠性。

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