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51. 发明授权

US08324046B2 Poly resistor and poly eFuse design for replacement gate technology 有权
标题翻译： Poly电阻和poly eFuse设计替代栅极技术
公开(公告)号：US08324046B2
公开(公告)日：2012-12-04
申请号：US13174368
申请日：2011-06-30
申请人： Kong-Beng Thei , Harry Chuang
发明人： Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8234
CPC分类号： H01L27/0629 , H01L23/5256 , H01L28/20 , H01L29/66545 , H01L29/66628 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation region, wherein the recess is defined by a concave surface of the isolation region; and forming a first gate structure over the substrate surface and a second gate structure over the concave surface of the isolation region.
摘要翻译：公开了制造半导体器件的方法。在一个实例中，一种方法包括在衬底上形成隔离区域，其中隔离区域从衬底表面向衬底延伸深度; 在所述隔离区域中形成凹部，其中所述凹部由所述隔离区域的凹面限定; 以及在所述衬底表面上形成第一栅极结构，以及在所述隔离区域的所述凹表面上方形成第二栅极结构。

52. 发明授权

US08143131B2 Method of fabricating spacers in a strained semiconductor device 有权
标题翻译：在应变半导体器件中制造间隔物的方法
公开(公告)号：US08143131B2
公开(公告)日：2012-03-27
申请号：US12415021
申请日：2009-03-31
申请人： Chen-Pin Hsu , Kong-Beng Thei , Harry Chuang
发明人： Chen-Pin Hsu , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823864 , H01L29/0847 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.
摘要翻译：本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成栅极叠层的侧壁上的栅极间隔物。

53. 发明申请

US20120045889A1 INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS 有权
标题翻译：在门窗最后一个过程中集成第一个接触结构
公开(公告)号：US20120045889A1
公开(公告)日：2012-02-23
申请号：US13286276
申请日：2011-11-01
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/28
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
摘要翻译：提供了一种提供基板的方法，在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。示例性接触特征是双重接触。

54. 发明授权

US08120086B2 Low leakage capacitors including portions in inter-layer dielectrics 有权
标题翻译：低漏电容器，包括层间电介质中的部分
公开(公告)号：US08120086B2
公开(公告)日：2012-02-21
申请号：US12331109
申请日：2008-12-09
申请人： Oscar M. K. Law , Kong-Beng Thei , Harry Chuang
发明人： Oscar M. K. Law , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/0629 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate including a first region and a second region; an insulation region in the second region of the semiconductor substrate; and an inter-layer dielectric (ILD) over the insulation region. A transistor is in the first region. The transistor includes a gate dielectric and a gate electrode over the gate dielectric. A first conductive line and a second conductive line are over the insulation region. The first conductive line and the second conductive line are substantially parallel to each other and extending in a first direction. A first metal line and a second metal line are in a bottom metal layer (M1) and extending in the first direction. The first metal line and the second metal line substantially vertically overlap the first conductive line and the second conductive line, respectively. The first metal line and the second metal line form two capacitor electrodes of a capacitor.
摘要翻译：集成电路结构包括：包括第一区域和第二区域的半导体衬底; 半导体衬底的第二区域中的绝缘区域; 和绝缘区域上的层间电介质（ILD）。晶体管处于第一区域。晶体管包括栅极电介质和位于栅极电介质上的栅电极。第一导线和第二导线在绝缘区上方。第一导线和第二导线基本上彼此平行并沿第一方向延伸。第一金属线和第二金属线位于底部金属层（M1）中并沿第一方向延伸。第一金属线和第二金属线分别基本上垂直地与第一导线和第二导线重叠。第一金属线和第二金属线形成电容器的两个电容器电极。

55. 发明授权

US08105929B2 Gate control and endcap improvement 有权
标题翻译：门控和端帽改进
公开(公告)号：US08105929B2
公开(公告)日：2012-01-31
申请号：US12193538
申请日：2008-08-18
申请人： Harry Chuang , Kong-Beng Thei
发明人： Harry Chuang , Kong-Beng Thei
IPC分类号： H01L21/38
CPC分类号： H01L21/28123 , H01L21/823437 , H01L27/0207 , H01L29/4966 , Y10S438/917
摘要： A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.
摘要翻译：形成半导体结构的方法包括以下步骤。在有源区中的衬底上形成栅介电层。栅极电极层形成在栅极介电层上。在栅电极层上形成第一光刻胶。蚀刻栅极电极层和电介质层，从而形成栅极结构和虚拟图案，其中虚拟图案中的至少一个具有活性区域中的至少一部分。第一张光刻胶被去除。形成覆盖栅极结构的第二光致抗蚀剂。去除不受第二光致抗蚀剂保护的虚拟图案。然后移除第二个光刻胶。

56. 发明授权

US08058119B2 Device scheme of HKMG gate-last process 有权
标题翻译： HKMG最终进程的设备方案
公开(公告)号：US08058119B2
公开(公告)日：2011-11-15
申请号：US12536878
申请日：2009-08-06
申请人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/66545
摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.
摘要翻译：本公开提供了制造半导体器件的金属栅叠层的方法。该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

57. 发明授权

US08039381B2 Photoresist etch back method for gate last process 有权
标题翻译：光栅蚀刻回路法最后一道工序
公开(公告)号：US08039381B2
公开(公告)日：2011-10-18
申请号：US12477618
申请日：2009-06-03
申请人： Chiung-Han Yeh , Chen-Pin Hsu , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Chen-Pin Hsu , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/42376 , H01L21/28079 , H01L21/28088 , H01L21/28105 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method is provided for fabricating a semiconductor device. The method includes providing a substrate including a dummy gate structure formed thereon, removing the dummy gate structure to form a trench, forming a first metal layer over the substrate to fill a portion of the trench, forming a protection layer in a remaining portion of the trench, removing a unprotected portion of the first metal layer, removing the protection layer from the trench, and forming a second metal layer over the substrate to fill the trench.
摘要翻译：提供了制造半导体器件的方法。该方法包括提供包括形成在其上的虚拟栅极结构的衬底，去除伪栅极结构以形成沟槽，在衬底上形成第一金属层以填充沟槽的一部分，在其中的一部分形成保护层去除所述第一金属层的未受保护部分，从所述沟槽移除所述保护层，以及在所述衬底上形成第二金属层以填充所述沟槽。

58. 发明申请

US20110233682A1 Reducing Device Performance Drift Caused by Large Spacings Between Active Regions 有权
标题翻译：降低活动区域之间大间距引起的设备性能漂移
公开(公告)号：US20110233682A1
公开(公告)日：2011-09-29
申请号：US13155251
申请日：2011-06-07
申请人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L27/088 , H01L27/092 , B82Y99/00
CPC分类号： H01L21/823475 , H01L21/31155 , H01L21/823412 , H01L21/823481 , H01L29/7846
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

59. 发明授权

US08017473B2 Modifying work function in PMOS devices by counter-doping 有权
标题翻译：通过反掺杂改进PMOS器件的功能
公开(公告)号：US08017473B2
公开(公告)日：2011-09-13
申请号：US12791656
申请日：2010-06-01
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L21/8238
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

60. 发明授权

US08008145B2 High-K metal gate structure fabrication method including hard mask 有权
标题翻译：高K金属栅极结构制造方法包括硬掩模
公开(公告)号：US08008145B2
公开(公告)日：2011-08-30
申请号：US12270466
申请日：2008-11-13
申请人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Provided is a method of fabricating a semiconductor device including a high-k metal gate structure. A substrate is provided including a dummy gate structure (e.g., a sacrificial polysilicon gate), a first and second hard mask layer overlie the dummy gate structure. In one embodiment, a strained region is formed on the substrate. After forming the strained region, the second hard mask layer may be removed. A source/drain region may be formed. An ILD layer is then formed on the substrate. A CMP process may planarize the ILD layer using the first hard mask layer as a stop layer. The CMP process may be continued to remove the first hard mask layer. The dummy gate structure is then removed and a metal gate provided.
摘要翻译：提供一种制造包括高k金属栅极结构的半导体器件的方法。提供了包括伪栅极结构（例如，牺牲多晶硅栅极），覆盖在虚拟栅极结构上的第一和第二硬掩模层的衬底。在一个实施例中，在基底上形成应变区域。形成应变区后，可以除去第二硬掩模层。可以形成源极/漏极区域。然后在衬底上形成ILD层。 CMP工艺可以使用第一硬掩模层作为停止层来平坦化ILD层。 CMP工艺可以继续去除第一硬掩模层。然后去除虚拟栅极结构并提供金属栅极。

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