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51. 发明申请

US20100231100A1 Cooling storage cabinet 审中-公开
标题翻译：冷却储藏柜
公开(公告)号：US20100231100A1
公开(公告)日：2010-09-16
申请号：US12308458
申请日：2007-06-14
申请人： Kiyoshi Kato , Etsuo Sugiyama , Masayuki Nishio , Daisuke Hiraki
发明人： Kiyoshi Kato , Etsuo Sugiyama , Masayuki Nishio , Daisuke Hiraki
IPC分类号： F25D23/00
CPC分类号： F25D21/14 , F25D2321/146
摘要： The present invention can include a cooling storage cabinet including a storage cabinet body having a side face, a drain head for draining water to the outside, the drain head protruding from the side face of the storage cabinet body, a vaporizing receptacle for collecting water from the drain pipe, the vaporizing receptacle being disposed below the drain head and having a face opposed to the side face of the storage cabinet body, and a heater for vaporizing the drained water. The vaporizing receptacle can includes a concavity formed on the face, the concavity being configured to form a layer of air between the side face of the storage cabinet body.
摘要翻译：本发明可以包括一个冷却储藏柜，它包括一个具有侧面的储存箱主体，用于向外部排水的排水头，从储藏箱主体的侧面突出的排水头，一个用于从排水管，蒸发容器设置在排水头下方并具有与储藏箱主体的侧面相对的面，以及用于蒸发排水的加热器。蒸发容器可以包括形成在表面上的凹部，该凹部构造成在储藏箱主体的侧面之间形成空气层。

52. 发明授权

US07714633B2 Limiter and semiconductor device using the same 有权
标题翻译：限制器和半导体器件使用相同
公开(公告)号：US07714633B2
公开(公告)日：2010-05-11
申请号：US10593577
申请日：2005-04-06
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： H03K5/00 , H01L23/62
CPC分类号： H01L27/1266 , G06K19/07735 , G06K19/07749 , H01L23/49855 , H01L27/0266 , H01L27/12 , H01L27/1214 , H01L27/13 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： By using a stacked gate transistor including a floating gate in a limiter, a threshold voltage Vth of the stacked gate transistor can be corrected by controlling the amount of charge accumulated in the floating gate of the stacked gate transistor even in the case where there are variations in the threshold voltage Vth of the stacked gate transistor.
摘要翻译：通过在限幅器中使用包括浮置栅极的层叠栅极晶体管，可以通过控制堆叠栅极晶体管的浮置栅极中累积的电荷量来校正层叠栅极晶体管的阈值电压Vth，即使在存在变化的情况下在层叠栅极晶体管的阈值电压Vth中。

53. 发明申请

US20100057660A1 OPERATION MANAGEMENT DEVICE, OPERATION MANAGEMENT METHOD, AND OPERATION MANAGEMENT PROGRAM 有权
标题翻译：操作管理设备，操作管理方法和操作管理程序
公开(公告)号：US20100057660A1
公开(公告)日：2010-03-04
申请号：US12530762
申请日：2008-03-04
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G06N5/02
CPC分类号： H04L41/0604 , G06F11/008 , G06F11/3452 , G06F2201/86 , H04L41/147
摘要： An operation management apparatus decides that newly-generated event data and previously-existing predictive event data match if the attribute values of the event data match the attribute values of the predictive event data excluding reference values. In such a case, the apparatus identifies individual filter information whose attribute values excluding reference values match the attribute values of the event data, and substitutes the attribute values of the event data for variables in each piece of individual filter information belonging to a group to which the individual filter information belongs, thereby generating predictive event data for each piece of individual filter information. The apparatus decides whether or not each piece of event data that is associated in a predictive event index with the group to which the individual filter information that matches the event data used for generating the predictive event data belongs satisfies the individual filter information of operation rule information corresponding to the group, and if satisfies, performs processing defined by the operation rule information.
摘要翻译：如果事件数据的属性值与除了参考值的预测事件数据的属性值相匹配，则操作管理装置判定新生成的事件数据和先前存在的预测事件数据相匹配。在这种情况下，该装置识别除了参考值的属性值与事件数据的属性值相匹配的单个过滤器信息，并且将属于其的每个单独过滤器信息中的变量的事件数据的属性值替换为各个过滤器信息属于，从而为每个单独的过滤器信息生成预测事件数据。该装置判定与预测事件索引相关联的每条事件数据是否与与用于生成预测事件数据的事件数据匹配的各个过滤器信息所对应的组满足操作规则信息的各个过滤器信息对应于组，并且如果满足，则执行由操作规则信息定义的处理。

54. 发明授权

US07652321B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07652321B2
公开(公告)日：2010-01-26
申请号：US11072632
申请日：2005-03-07
申请人： Tetsuji Yamaguchi , Kiyoshi Kato
发明人： Tetsuji Yamaguchi , Kiyoshi Kato
IPC分类号： H01L29/72
CPC分类号： H01L21/84 , H01L27/11526 , H01L27/11546 , H01L27/1203
摘要： In a process of manufacturing elements of different structures and characteristics on the same substrate at the same time, the number of steps is increased and complicated. In view of this, the invention provides a semiconductor device and a manufacturing process thereof in which elements of different structures are formed on the same substrate while reducing the number of steps. According to the invention, in accordance with a memory transistor that requires the largest number of steps when being formed among elements that forms a semiconductor memory device, other high speed transistor and high voltage transistor are efficiently manufactured. Thus, the number of steps is suppressed and a low cost semiconductor memory device can be manufactured.
摘要翻译：在同一基板上同时制造不同结构和特性的元件的过程中，台阶增加复杂。鉴于此，本发明提供了一种半导体器件及其制造方法，其中不同结构的元件形成在同一衬底上，同时减少了步骤数。根据本发明，根据在形成半导体存储器件的元件之间形成最大数量的步骤的存储晶体管时，有效地制造其它高速晶体管和高压晶体管。因此，抑制了步数，并且可以制造低成本的半导体存储器件。

55. 发明申请

US20090289341A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090289341A1
公开(公告)日：2009-11-26
申请号：US12468284
申请日：2009-05-19
申请人： Shunpei Yamazaki , Yoshiaki Oikawa , Hironobu Shoji , Yutaka Shionoiri , Kiyoshi Kato , Masataka Nakada
发明人： Shunpei Yamazaki , Yoshiaki Oikawa , Hironobu Shoji , Yutaka Shionoiri , Kiyoshi Kato , Masataka Nakada
IPC分类号： H01L23/02
CPC分类号： G06K19/07749 , G06K19/07735 , H01L27/1214 , H01L27/1218 , H01L27/1266 , H01L27/13 , H01Q1/38 , H01Q7/00
摘要： An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a semiconductor device with a high yield. A first insulator and a second insulator facing each other, a semiconductor integrated circuit and an antenna provided between the first insulator and the second insulator facing each other, a conductive shield provided on one surface of the first insulator, and a conductive shield provided on one surface of the second insulator are provided. The conductive shield provided on one surface of the first insulator and the conductive shield provided on one surface of the second insulator are electrically connected.
摘要翻译：目的是提供一种具有耐外部应力和静电放电的高度可靠的半导体器件，同时实现厚度和尺寸的减小。另一个目的是在制造过程中防止由于外部应力或静电放电而导致的形状不良和特性劣化，从而以高产率制造半导体器件。第一绝缘体和第二绝缘体彼此面对，半导体集成电路和设置在第一绝缘体和第二绝缘体之间彼此面对的天线，设置在第一绝缘体的一个表面上的导电屏蔽和设置在第一绝缘体上的导电屏蔽提供第二绝缘体的表面。设置在第一绝缘体的一个表面上的导电屏蔽和设置在第二绝缘体的一个表面上的导电屏蔽电连接。

56. 发明授权

US07596024B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07596024B2
公开(公告)日：2009-09-29
申请号：US11776973
申请日：2007-07-12
申请人： Kiyoshi Kato , Shunpei Yamazaki
发明人： Kiyoshi Kato , Shunpei Yamazaki
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C8/12 , G11C8/14 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/12 , H01L27/124
摘要： A highly-integrated nonvolatile memory. A memory cell array where plural memory cells are arranged in matrix in row and column directions, plural first and second word lines, and plural bit lines are included. Each of the plural memory cells includes a first memory transistor and a second memory transistor which are connected in series. A gate electrode of the first memory transistor is connected to the first word line, a gate electrode of the second memory transistor is connected to the second word line, one of source and drain regions of the first memory transistor is connected to the first bit line, and one of source and drain regions of the second memory transistor is connected to the second bit line. Each of the first bit line and the second bit line is provided in common for memory cells in columns which are adjacent to each other.
摘要翻译：高度集成的非易失性存储器。存储单元阵列，其中多个存储单元以行和列方向排列成矩阵，多个第一和第二字线以及多个位线。多个存储单元中的每一个包括串联连接的第一存储晶体管和第二存储晶体管。第一存储晶体管的栅电极连接到第一字线，第二存储晶体管的栅电极连接到第二字线，第一存储晶体管的源极和漏极区之一连接到第一位线并且第二存储晶体管的源极和漏极区中的一个连接到第二位线。第一位线和第二位线中的每一个被共同地设置在彼此相邻的列中的存储器单元。

57. 发明授权

US07583250B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07583250B2
公开(公告)日：2009-09-01
申请号：US10793822
申请日：2004-03-08
申请人： Kiyoshi Kato , Toshihiko Saito
发明人： Kiyoshi Kato , Toshihiko Saito
IPC分类号： G09G3/36
CPC分类号： G02F1/13338 , G02F1/13306 , G02F1/133305 , G02F1/133345 , G02F1/13439 , G02F1/13454 , G02F1/136213 , G02F1/1368 , G02F2201/123 , G06F3/0412 , G06F3/044 , G09G3/36 , H01L27/12 , H01L27/1214 , H01L27/1218 , H01L27/124 , H01L27/1255 , H01L27/1288 , H01L27/13 , H01L27/3244 , H01L29/78621 , H01L29/78645
摘要： A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.
摘要翻译：可变电容器由一对电极和位于基板之间的电极之间的电介质形成，并且通过用物理或电力改变可变电容器的电容来检测外部输入。具体地说，在同一衬底上设置可变电容器和读出放大器，读出放大器读取可变电容器的电容变化，并根据输入将信号发送到控制电路。

58. 发明申请

US20090216624A1 OPERATIONS MANAGEMENT APPARATUS, OPERATIONS MANAGEMENT SYSTEM, DATA PROCESSING METHOD, AND OPERATIONS MANAGEMENT PROGRAM 有权
标题翻译：操作管理装置，操作管理系统，数据处理方法和操作管理程序
公开(公告)号：US20090216624A1
公开(公告)日：2009-08-27
申请号：US12391445
申请日：2009-02-24
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G06Q10/00 , G06F17/10
CPC分类号： G06N5/02 , G06F11/3409 , G06F11/3447 , G06F11/3476 , G06Q10/0639
摘要： An operations management apparatus which acquires performance information for each of a plurality of performance items from a plurality of controlled units and manages operation of the controlled units includesa correlation model generation unit which derives a correlation function between a first element and a second element of the performance information, generates a correlation model between the first element and the second element based on the correlation function, and obtains the correlation model for each element pair of the performance information, anda model searching unit which searches for the correlation model for each element between an input element and an output element among elements of the performance information in series, and predicts a value of the output element from a value of the input element based on the searched correlation model.
摘要翻译：一种操作管理装置，其从多个受控单位取得多个演奏项目的演奏信息，并管理上述受控单位的动作，包括：相关模型生成部，其将第一，第二组合的相关函数，性能信息，基于相关函数产生第一元素和第二元素之间的相关模型，并获得每个元素对的性能信息的相关模型，以及模型搜索单元，其搜索每个元素之间的相关模型输入元素和输出元素，并且基于搜索到的相关模型从输入元素的值预测输出元素的值。

59. 发明申请

US20090206345A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090206345A1
公开(公告)日：2009-08-20
申请号：US12429200
申请日：2009-04-24
申请人： Kiyoshi Kato , Tadafumi Ozaki , Kohei Mutaguchi
发明人： Kiyoshi Kato , Tadafumi Ozaki , Kohei Mutaguchi
IPC分类号： H01L33/00
CPC分类号： H01L29/78621 , H01L27/12 , H01L27/1285 , H01L29/66757 , H01L29/78675
摘要： A semiconductor device having a display unit, which is small in size, suppresses the defect caused by the mounting of IC chips and the like on the substrate, and operates at a high speed. A semiconductor display unit and other circuit blocks are integrally formed on the substrate having an insulating surface by using a process for fabricating TFTs that realize a high degree of mobility. Concretely, there is employed a process for crystallizing a semiconductor active layer by using a continuously oscillating laser. Further, the process for crystallization relying upon the continuously oscillating laser is selectively effected for only those circuit blocks that must be operated at high speeds, thereby to realize a high production efficiency.
摘要翻译：具有尺寸小的显示单元的半导体器件抑制由于将IC芯片等安装在基板上而引起的缺陷，并且高速运转。通过使用实现高移动性的TFT的制造工艺，半导体显示单元和其它电路块一体地形成在具有绝缘表面的基板上。具体地，采用使用连续振荡激光使半导体活性层结晶的工艺。此外，仅依赖于必须以高速运转的电路块选择性地实现依赖于连续振荡激光的结晶工艺，从而实现高生产效率。

60. 发明授权

US07561476B2 Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory 有权
公开(公告)号：US07561476B2
公开(公告)日：2009-07-14
申请号：US11072198
申请日：2005-03-03
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G11C16/04
CPC分类号： G11C16/3472 , G11C16/3468 , G11C16/3481
摘要： Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier (102) that performs reading is connected to a switch which switches an operation voltage applied to a memory cell in accordance with a verify signal Sv, and the verify operation is finished concurrently with having the verify signal Sv switched. By obtaining such circuit construction and simultaneously performing writing/erasing and reading, it becomes possible to perform high-speed verify writing/erasing.

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