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51. 发明授权

US08009505B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08009505B2
公开(公告)日：2011-08-30
申请号：US12500023
申请日：2009-07-09
申请人： Hiromasa Noda
发明人： Hiromasa Noda
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , G11C7/1045 , G11C11/4074 , G11C11/408 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2207/2227
摘要： A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.
摘要翻译：半导体存储器件包括行控制电路块和列控制电路块，每个行控制电路块执行存储单元阵列上的访问控制，数据I / O电路块向存储单元阵列发送数据和从存储单元阵列接收数据;以及控制电路响应于将预定模式信号设置到模式寄存器，将行控制电路块，列控制电路块和数据I / O电路块的至少一部分改变为从待机状态变为有效状态。根据本发明，即使需要通过除了读取或写入操作之外的操作将预定的电路块转变为活动状态，也不需要总是将这些电路块设置为活动状态。

52. 发明申请

US20100110817A1 Semiconductor device and refreshing method 审中-公开
标题翻译：半导体器件和刷新方法
公开(公告)号：US20100110817A1
公开(公告)日：2010-05-06
申请号：US12588452
申请日：2009-10-15
申请人： Hiromasa Noda , Atsushi Fujikawa
发明人： Hiromasa Noda , Atsushi Fujikawa
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/18 , G11C2211/4067
摘要： A semiconductor device comprising a word line wired on a memory bank, a memory cell storing data provided in correspondence with the word line and a sense amplifier provided in correspondence with the word line, refreshing the memory cell corresponding to the word line selected by a row address that has been generated, including refresh counter 2 that generates a counter address corresponding to the row address and sequentially counts up the counter address, controller 1 that determines and outputs, upon receiving a refresh command instructing that a refresh operation be performed, first line number information and second line number information determining a number of word lines to be started based on the counter address and word line selector 3 that determines the row address according to the first line number information and the second line number information, and the counter address.
摘要翻译：一种半导体器件，包括布线在存储体上的字线，存储单元，存储与字线对应地提供的数据;以及读出放大器，与所述字线对应地设置，刷新与行相对应的字线对应的存储单元地址，包括生成与行地址相对应的计数器地址的刷新计数器2，并且在接收到指示执行刷新操作的刷新命令时，确定并输出确定并输出的控制器1，数字信息和第二行号码信息，以及根据第一行号码信息和第二行号码信息确定行地址的计数器地址和字线选择器3确定要开始的字线数量，以及计数器地址。

53. 发明申请

US20090201753A1 Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address 有权
标题翻译：半导体存储器件及其控制方法以及用于确定缺陷地址修复可能性的方法
公开(公告)号：US20090201753A1
公开(公告)日：2009-08-13
申请号：US12320892
申请日：2009-02-06
申请人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
发明人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
IPC分类号： G11C29/00 , G11C8/00 , G11C17/16
CPC分类号： G11C8/08 , G11C8/10 , G11C29/84
摘要： There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.
摘要翻译：提供有多个存储器垫，子字驱动器，其访问正常存储器单元，而不管请求访问的行地址是否是缺陷地址;子字驱动器，访问属于当行地址是缺陷地址时，由行地址指示的正常存储单元不同的存储器垫。根据本发明，正常存储单元和冗余存储单元属于彼此不同的存储器单元，从而可以在确定修复确定电路的操作的同时访问正常存储单元。

54. 发明授权

US07450446B2 Semiconductor memory device having delay circuit 有权
标题翻译：具有延迟电路的半导体存储器件
公开(公告)号：US07450446B2
公开(公告)日：2008-11-11
申请号：US11598566
申请日：2006-11-14
申请人： Hiromasa Noda , Hiroki Fujisawa
发明人： Hiromasa Noda , Hiroki Fujisawa
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C29/026 , G11C29/028 , G11C29/50012
摘要： Disclosed is a semiconductor memory device configured to delay an input signal in accordance with a clock signal having a clock period. The semiconductor memory device comprises a reference signal generator and a delay circuit. The reference signal generator configured to generate a reference signal in accordance with the clock signal. The reference signal indicates a reference delay time representing the clock period. The delay circuit configured to delay input signal for a delay time to generate a delayed signal in accordance with the reference signal. The delay time is obtainable by multiplying the reference delay time by a positive integer.
摘要翻译：公开了一种被配置为根据具有时钟周期的时钟信号来延迟输入信号的半导体存储器件。半导体存储器件包括参考信号发生器和延迟电路。参考信号发生器被配置为根据时钟信号产生参考信号。参考信号表示表示时钟周期的参考延迟时间。延迟电路被配置为延迟输入信号一段延迟时间，以根据该参考信号产生延迟的信号。延迟时间可以通过将参考延迟时间乘以正整数来获得。

55. 发明申请

US20080169840A1 Semiconductor device having a pseudo power supply wiring 有权
标题翻译：具有伪电源布线的半导体装置
公开(公告)号：US20080169840A1
公开(公告)日：2008-07-17
申请号：US11878209
申请日：2007-07-23
申请人： Junichi Hayashi , Hiromasa Noda
发明人： Junichi Hayashi , Hiromasa Noda
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A semiconductor device including an AND-NOR composite gate of which AND unit is supplied with input signals IN and VDD and NOR unit is supplied with an inverted signal EB of an enable signal E, and an AND-NOR composite gate of which AND unit is supplied with an input signal INB and an enable signal E and NOR unit is supplied with VSS. These gates are inserted into a path to which the input signals IN and INB are supplied. Thereby, a symmetric property of a complimentary signal can be retained. Further, outputs of the AND-NOR composite gates are fixed irrespective of a logical level of the enable signal E. Thus, a sub-threshold current also is inhibited.
摘要翻译：一个包括AND和NOR复合栅极的半导体器件，其中AND单元被提供有输入信号IN和VDD以及NOR单元，其中提供有使能信号E的反相信号EB和AND单元的AND-NOR复合栅极提供有输入信号INB，使能信号E和NOR单元提供VSS。这些门被插入到提供输入信号IN和INB的路径中。由此，能够保持互补信号的对称性。此外，与使能信号E的逻辑电平无关地，AND-NOR复合栅极的输出是固定的。因此，也会抑制次阈值电流。

56. 发明授权

US06414530B2 Semiconductor integrated circuit device, semiconductor memory system and clock synchronous circuit 失效
标题翻译：半导体集成电路器件，半导体存储器系统和时钟同步电路
公开(公告)号：US06414530B2
公开(公告)日：2002-07-02
申请号：US09832019
申请日：2001-04-11
申请人： Hiromasa Noda , Masakazu Aoki , Hitoshi Tanaka , Hideyuki Aoki
发明人： Hiromasa Noda , Masakazu Aoki , Hitoshi Tanaka , Hideyuki Aoki
IPC分类号： H03K1126
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/22 , G11C7/222 , H03K5/133 , H03K5/135 , H03K5/1504
摘要： A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.
摘要翻译：格子状延迟电路被配置为其中分别设置有用于分别耦合输入到第一和第二输入端子的两个输入信号的阻抗元件的多个逻辑门电路，并且分别形成通过将输入到第一和第二输入端的输入信号反相而获得的输出信号和第二信号被使用以在第一信号传送方向和第二信号传送方向上以格子形式布置。输入时钟信号在第一信号传送方向上被连续地延迟，然后输入到从第一信号传输方向看到的从第一到最后的逻辑门电路。输出信号从放置在至少多个级的逻辑门电路的输出端获得，如第二信号传送方向所示，并且被布置在第一信号传送方向。

57. 发明授权

US06385100B2 Semiconductor memory device with improved column selecting operation 有权
标题翻译：具有改进的列选择操作的半导体存储器件
公开(公告)号：US06385100B2
公开(公告)日：2002-05-07
申请号：US09789753
申请日：2001-02-22
申请人： Hiromasa Noda , Youji Idei , Osamu Nagashima , Tetsuo Ado
发明人： Hiromasa Noda , Youji Idei , Osamu Nagashima , Tetsuo Ado
IPC分类号： G11C700
CPC分类号： G11C29/84 , G11C7/1027 , G11C8/04 , G11C11/4087
摘要： A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.
摘要翻译：一种半导体存储器件具有列地址解码器，它包括分别对应于高阶和低阶地址的第一和第二预解码器，用于使用第二预解码器的输出信号作为初始值的移位寄存器，以及输出电路，用于根据动作模式选择第二预解码器的输出信号或移位寄存器的输出信号。选择信号由第一预解码器的输出信号和通过输出电路的输出信号形成。移位寄存器包括用于偶数地址的第一移位寄存器和奇数地址的第二移位寄存器，并且基于顺序动作和交错动作形成位线的两组连续选择信号通过组合其上下移动动作的初始值。

58. 发明授权

US5408116A Grooved gate transistor having source and drain diffused layers with specified groove corner shape 失效
标题翻译：沟槽栅极晶体管，具有指定槽角形状的源极和漏极扩散层
公开(公告)号：US5408116A
公开(公告)日：1995-04-18
申请号：US105330
申请日：1993-08-09
申请人： Junko Tanaka , Toru Toyabe , Shin'ichiro Kimura , Hiromasa Noda , Sigeo Ihara , Kiyoo Itoh , Yasushi Gotoh
发明人： Junko Tanaka , Toru Toyabe , Shin'ichiro Kimura , Hiromasa Noda , Sigeo Ihara , Kiyoo Itoh , Yasushi Gotoh
IPC分类号： H01L29/78 , B82B1/00 , H01L27/108 , H01L29/06 , H01L29/12 , H01L29/423
CPC分类号： H01L29/125 , B82Y10/00 , H01L27/10808 , H01L29/78
摘要： A finely structured grooved gate transistor of which the threshold voltage does not decrease in spite of the small size and of which the threshold voltage of the transistor can be adjusted by shape. The shape of a groove corner of the transistor as a semiconductor device is contained in a concentric circle having a radius of curvature r.+-.L/5 (L: channel length) and the radius of curvature r, i.e., the geometric parameter has a relationship with the doping concentration as shown in FIG. 1B. Alternatively, the average (a+b)/2 (geometric parameter) of the sum of the two sides opposite the right angle of a right triangle formed of a straight line in contact with the gate bottom in parallel to the substrate surface of a grooved gate transistor, a perpendicular line to the substrate bottom surface from the source and drain ends at a portion formed with a channel and a straight line in contact with the groove corner has a relationship with the doping concentration as shown in FIG. 1B. The threshold voltage is not reduced even when the channel length is decreased by adjusting the groove shape and the doping concentration.
摘要翻译：尽管尺寸小，但是其晶体管的阈值电压可以通过形状来调整，其中阈值电压不降低的精细结构的开槽栅极晶体管。作为半导体器件的晶体管的槽角的形状包含在具有曲率半径r +/- L / 5（L：沟道长度）和曲率半径r的同心圆中，即几何参数具有与掺杂浓度的关系如图1所示。 1B。或者，平行于沟槽的基板表面的与栅极底部接触的直线形成的直角三角形的直角相反的两侧的平均（a + b）/ 2（几何参数）栅极晶体管，在形成有沟道的部分处的源极和漏极端部处的与衬底底表面的垂直线和与沟槽角接触的直线与图1所示的掺杂浓度具有关系。 1B。即使通过调整沟槽形状和掺杂浓度来减小沟道长度，阈值电压也不会降低。

59. 发明授权

US09183949B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09183949B2
公开(公告)日：2015-11-10
申请号：US13324567
申请日：2011-12-13
申请人： Hiromasa Noda , Toshio Ninomiya
发明人： Hiromasa Noda , Toshio Ninomiya
IPC分类号： G11C29/02
CPC分类号： G11C29/028 , G11C29/021 , G11C29/023
摘要： A device includes a decoder, a selector, and a plurality of registers. The decoder is configured to generate a plurality of test signals. The selector is coupled to the decoder. The selector is configured to sequentially select a test signal from the plurality of test signals and to sequentially output the test signal selected. The plurality of registers is coupled in series to each other. The plurality of registers includes a first stage register. The first stage register is coupled to the selector to sequentially receive the test signal from the selector.
摘要翻译：一种装置包括解码器，选择器和多个寄存器。解码器被配置为产生多个测试信号。选择器耦合到解码器。选择器被配置为从多个测试信号中顺序地选择测试信号，并且顺序地输出所选择的测试信号。多个寄存器彼此串联耦合。多个寄存器包括第一级寄存器。第一级寄存器耦合到选择器以顺序地从选择器接收测试信号。

60. 发明授权

US08891318B2 Semiconductor device having level shift circuit 有权
标题翻译：具有电平移位电路的半导体器件
公开(公告)号：US08891318B2
公开(公告)日：2014-11-18
申请号：US13286665
申请日：2011-11-01
申请人： Takenori Sato , Yoji Idei , Hiromasa Noda
发明人： Takenori Sato , Yoji Idei , Hiromasa Noda
IPC分类号： G11C7/10 , G11C7/22 , H03K19/0175 , G11C11/4076 , G11C29/02 , H03K3/356 , G11C29/50 , G11C11/4093
CPC分类号： G11C11/4093 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C29/022 , G11C29/025 , G11C29/028 , G11C29/50008 , H03K3/356104
摘要： A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.
摘要翻译：半导体器件包括：具有基本相同的电路配置的两个电平移位电路; 输入电路，分别向电平移位电路提供互补输入信号; 以及输出电路，其将从电平移位电路输出的互补输出信号转换为同相信号，然后使同相信号短路。根据本发明，使用具有基本相同电路结构的两电平移位电路，并且从电平移位电路输出的互补输出信号在短路之前被转换为同相信号。由于电平移位电路之间的操作速度的差异，几乎不会发生任何直流电流的发生。

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