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51. 发明申请

US20100117160A1 POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY 有权
标题翻译：极性依赖开关电感式记忆
公开(公告)号：US20100117160A1
公开(公告)日：2010-05-13
申请号：US12407823
申请日：2009-03-20
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
IPC分类号： H01L29/00 , H01L21/425
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.
摘要翻译：描述了用于电阻读出存储器的极性依赖开关。存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。半导体晶体管包括形成在基板上的栅极元件。半导体晶体管包括源极触点和位触点。门元件电连接源触点和触点触点。电阻式感测存储单元电连接到位触点。源极接触和位触点用掺杂剂材料非对称地注入。

52. 发明申请

US20100110765A1 Non-Volatile Memory Cell with Programmable Unipolar Switching Element 有权
标题翻译：具有可编程单极性开关元件的非易失性存储单元
公开(公告)号：US20100110765A1
公开(公告)日：2010-05-06
申请号：US12497964
申请日：2009-07-06
申请人： Wei Tian , Nurul Amin , Insik Jin , Ming Sun , Venu Vaithyanathan , YoungPil Kim , Chulmin Jung
发明人： Wei Tian , Nurul Amin , Insik Jin , Ming Sun , Venu Vaithyanathan , YoungPil Kim , Chulmin Jung
IPC分类号： G11C11/14 , G11C11/00 , G11C11/40
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/76
摘要： A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.
摘要翻译：公开了一种具有可编程单极开关元件的非易失性存储单元，以及编程存储器元件的方法。在一些实施例中，存储单元包括与可编程单极性电阻感测开关元件串联连接的可编程双极性电阻读出存储元件。通过在所选择的方向上通过单元施加选择的写入电流将存储元件编程为所选择的电阻状态，其中通过沿第一方向的写入电流来编程第一电阻电平，并且其中第二电阻电平被编程通过在相反的第二方向上的写入电流。开关元件被编程为所选择的电阻水平以便于访问存储元件的所选择的电阻状态。

53. 发明申请

US20100091549A1 Non-Volatile Memory Cell with Complementary Resistive Memory Elements 有权
标题翻译：具有互补电阻记忆元件的非易失性存储单元
公开(公告)号：US20100091549A1
公开(公告)日：2010-04-15
申请号：US12501140
申请日：2009-07-10
申请人： Hyung-Kyu Lee , Young Pil Kim , Chulmin Jung
发明人： Hyung-Kyu Lee , Young Pil Kim , Chulmin Jung
IPC分类号： G11C11/00 , G11C11/14 , G11C7/00
CPC分类号： G11C13/0069 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C2013/0042 , G11C2013/0078 , G11C2013/0088 , G11C2213/79
摘要： A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current in a selected direction through the memory cell.
摘要翻译：非易失性存储单元和向其写入数据的方法。根据一些实施例，存储器单元包括被配置为同时存储互补的编程电阻状态的第一和第二电阻性存储元件（RME）。第一RME被编程为第一电阻状态，并且通过在所选择的方向上通过存储器单元施加公共写入电流，将第二RME同时编程为第二电阻状态。

54. 发明授权

US07433249B2 Apparatus with equalizing voltage generation circuit and methods of use 有权
标题翻译：具有均衡电压产生电路和使用方法的装置
公开(公告)号：US07433249B2
公开(公告)日：2008-10-07
申请号：US11347961
申请日：2006-02-06
申请人： Chulmin Jung
发明人： Chulmin Jung
IPC分类号： G11C5/14
CPC分类号： G11C11/4094
摘要： A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced by a feedback and control loop of the equalization voltage generator. The feedback and control loop includes a reference generator circuit to produce a stable, internal reference signal that is clamped at a maximum reference voltage. A comparator of the feedback and control loop compares the internal reference signal with a second voltage, which is proportional to the first voltage. The comparator causes the oscillator to turn on when the second voltage is lower than the reference voltage, and causes the oscillator to turn off when the second voltage is higher than the reference voltage.
摘要翻译：存储器件包括均衡电压发生器。均衡电压发生器包括振荡器和电荷泵以产生第一电压，其可以用作互补数字线对的均衡电压。振荡器由均衡电压发生器的反馈和控制回路产生的振荡器控制信号控制。反馈和控制回路包括参考发生器电路，以产生稳定的内部参考信号，其被钳位在最大参考电压。反馈和控制环路的比较器将内部参考信号与第一电压成比例的第二电压进行比较。当第二电压低于参考电压时，比较器使振荡器导通，并且当第二电压高于参考电压时使振荡器关断。

55. 发明授权

US08617952B2 Vertical transistor with hardening implatation 有权
标题翻译：垂直晶体管与硬化插入
公开(公告)号：US08617952B2
公开(公告)日：2013-12-31
申请号：US12891966
申请日：2010-09-28
申请人： Young Pil Kim , Hyung-Kew Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
发明人： Young Pil Kim , Hyung-Kew Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
IPC分类号： H01L21/336
CPC分类号： H01L45/1233 , H01L27/228 , H01L27/2454 , H01L45/1206
摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.
摘要翻译：一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱状晶体管。然后将硬化物质注入垂直柱晶体管顶表面。然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

56. 发明授权

US08289751B2 Non-volatile memory cell with programmable unipolar switching element 有权
标题翻译：具有可编程单极开关元件的非易失性存储单元
公开(公告)号：US08289751B2
公开(公告)日：2012-10-16
申请号：US13117849
申请日：2011-05-27
申请人： Wei Tian , Nurul Amin , Insik Jin , Ming Sun , Venu Vaithyanathan , YoungPil Kim , Chulmin Jung
发明人： Wei Tian , Nurul Amin , Insik Jin , Ming Sun , Venu Vaithyanathan , YoungPil Kim , Chulmin Jung
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/76
摘要： A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.
摘要翻译：公开了一种具有可编程单极开关元件的非易失性存储单元，以及编程存储器元件的方法。在一些实施例中，存储单元包括与可编程单极性电阻感测开关元件串联连接的可编程双极性电阻读出存储元件。通过在所选择的方向上通过单元施加选择的写入电流将存储元件编程为所选择的电阻状态，其中通过沿第一方向的写入电流来编程第一电阻电平，并且其中第二电阻电平被编程通过在相反的第二方向上的写入电流。开关元件被编程为所选择的电阻水平以便于访问存储元件的所选择的电阻状态。

57. 发明授权

US08183126B2 Patterning embedded control lines for vertically stacked semiconductor elements 有权
标题翻译：为垂直堆叠的半导体元件绘制嵌入式控制线
公开(公告)号：US08183126B2
公开(公告)日：2012-05-22
申请号：US12502178
申请日：2009-07-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L21/30
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

58. 发明申请

US20120074488A1 VERTICAL TRANSISTOR WITH HARDENING IMPLATATION 有权
标题翻译：具硬化强度的垂直晶体管
公开(公告)号：US20120074488A1
公开(公告)日：2012-03-29
申请号：US12891966
申请日：2010-09-28
申请人： Young Pil Kim , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
发明人： Young Pil Kim , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L45/1233 , H01L27/228 , H01L27/2454 , H01L45/1206
摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.
摘要翻译：一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱晶体管。然后将硬化物质注入垂直柱晶体管顶表面。然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

59. 发明申请

US20120039112A1 Hierarchical Cross-Point Array of Non-Volatile Memory 有权
标题翻译：非易失性存储器的分层交叉点阵列
公开(公告)号：US20120039112A1
公开(公告)日：2012-02-16
申请号：US13280109
申请日：2011-10-24
申请人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： A01H6/14 , A01H5/02
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

60. 发明申请

US20120039111A1 POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY 有权
标题翻译：极性依赖开关电感式记忆
公开(公告)号：US20120039111A1
公开(公告)日：2012-02-16
申请号：US13278334
申请日：2011-10-21
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
IPC分类号： G11C11/00 , H01L29/78 , H01L45/00
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
摘要翻译：存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。半导体晶体管包括形成在基板上的栅极元件。半导体晶体管包括源极触点和位触点。门元件电连接源触点和触点触点。电阻读出存储单元电连接到位触点。源触点被更多地注入掺杂剂材料，然后进行位接触。

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