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51. 发明申请

US20080284460A1 METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION 失效
标题翻译：用于统计CMOS器件特征的方法和装置
公开(公告)号：US20080284460A1
公开(公告)日：2008-11-20
申请号：US12141862
申请日：2008-06-18
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
IPC分类号： G01R31/36
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
摘要翻译：使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。然后通过将表示线性关系的线的斜率除以激励电压来导出电容。可以对不同的电子设备进行测试，包括晶体管和互连结构。

52. 发明授权

US07298193B2 Methods and arrangements to adjust a duty cycle 有权
标题翻译：调整工作周期的方法和安排
公开(公告)号：US07298193B2
公开(公告)日：2007-11-20
申请号：US11377507
申请日：2006-03-16
申请人： Kanak B. Agarwal , Robert K. Montoye
发明人： Kanak B. Agarwal , Robert K. Montoye
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565
摘要： Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correction module may compare the frequencies of the detector signals to generate the delay signal. In some embodiments, once the duty cycle of the output clock signal reaches the desired duty cycle such as fifty percent, the correction module may be turned off.
摘要翻译：实施例可以包括占空比控制器，用于基于延迟信号和输入时钟信号来调整时钟信号的占空比。占空比检测器可以基于输出信号的占空比来确定具有频率的信号，并且校正模块可以比较检测器信号的频率以产生延迟信号。在一些实施例中，一旦输出时钟信号的占空比达到期望的占空比（例如百分之五十），则校正模块可以被关断。

53. 发明授权

US08903715B2 High bandwidth parsing of data encoding languages 有权
标题翻译：高带宽解析数据编码语言
公开(公告)号：US08903715B2
公开(公告)日：2014-12-02
申请号：US13464384
申请日：2012-05-04
申请人： Kanak B. Agarwal
发明人： Kanak B. Agarwal
IPC分类号： G06F17/28 , G06F17/20 , G06F17/27 , G06F17/21 , G10L21/00
CPC分类号： G06F17/272
摘要： A mechanism is provided for accelerating data exchange language parsing. An input data stream is loaded into a first in, first out (FIFO) memory. A tokenization bit corresponding to a next byte to be read is extracted from a FIFO. A determination is made as to whether the tokenization bit corresponding to the next byte to be read from the FIFO indicates a control character or a non-control character located in an associated FIFO memory location in the FIFO. Responsive to the tokenization bit indicating the control character, the control character that causes a state change in a state machine is processed. Responsive to the tokenization bit indicating the non-control character, a length associated with the tokenized bit is identified and a set of non-control characters that do not cause a state change in the state machine are processed based on the length associated with the tokenized bit.
摘要翻译：提供了一种加速数据交换语言解析的机制。输入数据流被加载到先进先出（FIFO）存储器中。从FIFO中提取与要读取的下一个字节对应的令牌化位。确定与从FIFO读取的下一个字节相对应的标记位是否指示位于FIFO中的相关FIFO存储器位置中的控制字符或非控制字符。响应于表示控制字符的标记位，处理导致状态机状态变化的控制字符。响应于指示非控制字符的标记位，识别与标记化位相关联的长度，并且基于与标记化位相关联的长度来处理在状态机中不导致状态改变的一组非控制字符位。

54. 发明申请

US20130147644A1 High Bandwidth Decompression of Variable Length Encoded Data Streams 有权
标题翻译：可变长度编码数据流的高带宽减压
公开(公告)号：US20130147644A1
公开(公告)日：2013-06-13
申请号：US13555547
申请日：2012-07-23
申请人： Kanak B. Agarwal , Harm P. Hofstee , Damir A. Jamsek , Andrew K. Martin
发明人： Kanak B. Agarwal , Harm P. Hofstee , Damir A. Jamsek , Andrew K. Martin
IPC分类号： H03M7/40
CPC分类号： H03M7/30
摘要： Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.
摘要翻译：提供用于解码可变长度编码数据流的机制。数据处理系统的解码器接收数据的输入行。输入数据行是可变长度编码数据流的一部分。解码器确定输入数据行的位溢出量到下一个输入数据行。解码器根据确定的位溢出量将对准数据的输入行开始于符号边界。解码器对对齐的输入数据行进行标记，以生成一组令牌。每个令牌对应于对齐的下一个输入数据行中的编码符号。解码器基于该组令牌生成数据的输出字。数据的输出字对应于原始数据集中的数据字。

55. 发明授权

US08415077B2 Simultaneous optical proximity correction and decomposition for double exposure lithography 有权
标题翻译：用于双曝光光刻的同时光学邻近校正和分解
公开(公告)号：US08415077B2
公开(公告)日：2013-04-09
申请号：US12856208
申请日：2010-08-13
申请人： Kanak B. Agarwal , Shayak Banerjee
发明人： Kanak B. Agarwal , Shayak Banerjee
IPC分类号： G03F1/36 , G06F17/50
CPC分类号： G03F7/70433 , G03F1/36 , G03F7/70441 , G03F7/70466
摘要： A mechanism is provided for simultaneous optical proximity correction (OPC) and decomposition for double exposure lithography. The mechanism begins with two masks that are equal to each other and to the target. The mechanism simultaneously optimizes both masks to obtain a wafer image that both matches the target and is robust to process variations. The mechanism develops a lithographic cost function that optimizes for contour fidelity as well as robustness to variation. The mechanism minimizes the cost function using gradient descent. The gradient descent works on analytically evaluating the derivative of the cost function with respect to mask movement for both masks. It then moves the masks by a fraction of the derivative.
摘要翻译：提供了用于同时光学邻近校正（OPC）和用于双曝光光刻的分解的机制。该机制以两个彼此相等并且与目标相同的掩模开始。该机制同时优化两个掩模以获得两者匹配目标并且对于处理变化是鲁棒的晶片图像。该机制开发出光刻成本函数，优化轮廓保真度以及变化的鲁棒性。该机制使用梯度下降最小化成本函数。梯度下降用于分析评估两个掩模相对于掩模移动的成本函数的导数。然后将掩模移动一部分衍生物。

56. 发明申请

US20120260223A1 Retargeting for Electrical Yield Enhancement 失效
标题翻译：重新定位电收益增强
公开(公告)号：US20120260223A1
公开(公告)日：2012-10-11
申请号：US13526984
申请日：2012-06-19
申请人： Kanak B. Agarwal
发明人： Kanak B. Agarwal
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting.
摘要翻译：提供了用于光刻布局的电屈服增强重定向的机制。对一组目标图案执行光学邻近校正，以便产生一组光学邻近校正掩模形状。针对所述一组光学邻近校正掩模形状中的每一个生成一组光刻轮廓。确定一组目标图案中的一组形状中的至少一种形状的电屈服敏感度。还基于形状的电屈服敏感度来确定该组形状中的至少一个形状中的每一个的重定向的量和方向。基于重定向的数量和方向，为至少一个形状中的每个形状生成具有重定向边缘的新集合的目标图案。

57. 发明授权

US08136079B2 Effective gate length circuit modeling based on concurrent length and mobility analysis 有权
公开(公告)号：US08136079B2
公开(公告)日：2012-03-13
申请号：US13187201
申请日：2011-07-20
申请人： Kanak B. Agarwal , Vivek Joshi
发明人： Kanak B. Agarwal , Vivek Joshi
IPC分类号： G06F9/455 , G06F17/50 , G06F11/22
CPC分类号： G06F17/5036
摘要： Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.

58. 发明授权

US08120356B2 Measurement methodology and array structure for statistical stress and test of reliabilty structures 失效
标题翻译：统计应力的测量方法和阵列结构以及可靠性结构的测试
公开(公告)号：US08120356B2
公开(公告)日：2012-02-21
申请号：US12482999
申请日：2009-06-11
申请人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
IPC分类号： G01V3/00
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译：在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛。在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。

59. 发明申请

US20110119642A1 Simultaneous Photolithographic Mask and Target Optimization 有权
标题翻译：同时光刻掩模和目标优化
公开(公告)号：US20110119642A1
公开(公告)日：2011-05-19
申请号：US12619742
申请日：2009-11-17
申请人： Kanak B. Agarwal , Shayak Banerjee , Damir A. Jamsek
发明人： Kanak B. Agarwal , Shayak Banerjee , Damir A. Jamsek
IPC分类号： G06F17/50
CPC分类号： G03F7/705 , G03F1/36
摘要： A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more lithographic contours. A mask and target movement module analytically evaluates a direction for mask and target movement thereby forming a plurality of pairs of mask and target movements. The mask and target movement module identifies a best pair of mask and target movements from the plurality of mask and target movements that minimizes a weighted cost function. A shape adjustment module adjusts at least one of a target shape or the mask shape based on the best pair of mask and target movements.
摘要翻译：提供了用于同时光刻掩模和目标优化（SMATO）的机制。光刻模拟器在晶片上产生掩模形状的图像，从而形成一个或多个平版印刷轮廓。掩模和目标移动模块分析地评估掩模和目标移动的方向，从而形成多对掩模和目标移动。掩模和目标移动模块从多个掩模和目标移动中识别出最佳化加权成本函数的最佳对掩模和目标移动。形状调整模块基于最佳的一对掩模和目标移动来调整目标形状或掩模形状中的至少一个。

60. 发明授权

US07546519B2 Method and apparatus for detecting and correcting soft-error upsets in latches 失效
标题翻译：在锁存器中检测和校正软错误的方法和装置
公开(公告)号：US07546519B2
公开(公告)日：2009-06-09
申请号：US11560420
申请日：2006-11-16
申请人： Kanak B. Agarwal
发明人： Kanak B. Agarwal
IPC分类号： H04L1/08
CPC分类号： G01R31/31816 , G01R31/318541 , G01R31/318569 , G06F11/1008
摘要： An error detection circuit for a latch precharges two dynamic nodes whose discharge paths are gated by true and complement storage nodes of the latch, such that one and only one of the dynamic nodes always discharges when the clock signal transitions from an active state to an inactive state. If a soft error flips the contents of the latch during storage mode the other dynamic node will discharge. A gate having inputs coupled to the dynamic nodes produces an error signal when both nodes have discharged. The error signal can then be used to select between true and complement outputs of the latch. The invention can be implemented in a more robust embodiment which examines the outputs of two error detection circuits to generate a combined error signal that ensures against false error detection when an upset occurs within one of the detection circuits.
摘要翻译：用于锁存器的错误检测电路对两个动态节点进行预充电，其放电路径由锁存器的真实存储节点和补码存储节点门控，使得当时钟信号从活动状态转换到非活动状态时，动态节点中只有一个总是放电州。如果在存储模式期间软错误翻转锁存器的内容，则另一个动态节点将放电。具有耦合到动态节点的输入的门在两个节点已经放电时产生误差信号。然后，误差信号可用于在锁存器的真和输出之间进行选择。本发明可以在更鲁棒的实施例中实现，该实施例检查两个错误检测电路的输出以产生组合误差信号，当在一个检测电路内发生不适时，确保防止错误检测。

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