专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20070147099A1 Electronic circuits utilizing normally-on junction field-effect transistor 审中-公开
公开(公告)号：US20070147099A1
公开(公告)日：2007-06-28
申请号：US11708325
申请日：2007-02-21
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H02M7/537
CPC分类号： H02M3/158 , H02M3/155 , H03K17/063 , H03K17/6871 , H03K17/693 , H03K2017/6875
摘要： Electronic circuits use low-cost depletion-mode JFET to serve as power switch. Since depletion-mode JFET has smaller conductive resistance and is majority carrier device, the energy loss is less when current flows through the depletion-mode JFET, and faster switching speed is obtained, thereby enhancing the efficiency of the electronic circuits.

52. 发明申请

US20070126057A1 Lateral DMOS device insensitive to oxide corner loss 审中-公开
标题翻译：侧面DMOS器件对氧化物角损失不敏感
公开(公告)号：US20070126057A1
公开(公告)日：2007-06-07
申请号：US11605438
申请日：2006-11-29
申请人： Jing-Meng Liu , Hung-Der Su
发明人： Jing-Meng Liu , Hung-Der Su
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0619 , H01L29/0653 , H01L29/0661 , H01L29/0878
摘要： In a lateral DMOS device which has a drain diffusion region, an insulator is provided on the drain diffusion region. The insulator is helpful to reduce the lateral electric field under silicon surface. The gate of the DMOS does not overlap with the insulator over the drain diffusion region such that the lateral DMOS device is insensitive to oxide corner loss.
摘要翻译：在具有漏极扩散区域的横向DMOS器件中，在漏极扩散区域上设置绝缘体。绝缘子有助于减小硅表面下的横向电场。 DMOS的栅极不与漏极扩散区域上的绝缘体重叠，使得侧向DMOS器件对氧化物角损失不敏感。

53. 发明申请

US20060126237A1 Booster power management integrated circuit chip with ESD protection between output pads thereof 失效
标题翻译：增压器电源管理集成电路芯片，其输出焊盘之间具有ESD保护
公开(公告)号：US20060126237A1
公开(公告)日：2006-06-15
申请号：US11154175
申请日：2005-06-15
申请人： Hung-Der Su , Jing-Meng Liu , Chiang-Yung Ku
发明人： Hung-Der Su , Jing-Meng Liu , Chiang-Yung Ku
IPC分类号： H02H9/00
CPC分类号： H02M3/155 , H02M1/32 , H03K17/08142 , H03K17/0822
摘要： A booster power management integrated circuit chip includes first and second output pads, a transistor switch coupled between the first and second output pads and having a gate, and a trigger circuit coupled between the first and second output pads and further coupled to the gate of the transistor switch. The trigger circuit drives the transistor switch to conduct when an instantaneous voltage larger than a trigger voltage level is present between the first and second output pads so as to enable electric current to flow through the transistor switch.
摘要翻译：升压电力管理集成电路芯片包括第一和第二输出焊盘，耦合在第一和第二输出焊盘之间并具有栅极的晶体管开关，以及耦合在第一和第二输出焊盘之间的触发电路，并进一步耦合到晶体管开关当在第一和第二输出焊盘之间存在大于触发电压电平的瞬时电压时，触发电路驱动晶体管开关导通，以使电流流过晶体管开关。

54. 发明申请

US20060279331A1 Tri-state output logic with zero quiescent current by one input control 失效
标题翻译：具有零静态电流的三态输出逻辑由一个输入控制
公开(公告)号：US20060279331A1
公开(公告)日：2006-12-14
申请号：US11217341
申请日：2005-09-02
申请人： Shui-Mu Lin , Chien-Sheng Chen , Nien-Hui Kung , Der-Jiunn Wang , Jing-Meng Liu , Wei-Hsin Wei
发明人： Shui-Mu Lin , Chien-Sheng Chen , Nien-Hui Kung , Der-Jiunn Wang , Jing-Meng Liu , Wei-Hsin Wei
IPC分类号： H03K19/00
CPC分类号： G06F1/26
摘要： A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.
摘要翻译：提出了根据输入节点的高，低或浮动产生三态逻辑输出的电压产生电路。本电压发生电路包括：产生多个脉冲的脉冲发生电路; 一个电压选择电路，具有耦合在公共源极上的一对NMOS晶体管，NMOS晶体管的每个漏极分别耦合到电流源，NMOS晶体管的两个栅极耦合到输入节点，并且NMOS晶体管的成对漏极产生一对电压输出; 多个触发器，其耦合到NMOS晶体管的漏极以根据脉冲锁定NMOS晶体管的电压输出; 内部电压产生单元耦合到输入节点以提供浮动电压电平; 以及由用于控制电压选择电路的正常操作的脉冲控制的多个开关以及内部电压产生单元与输入节点之间的导通。

55. 发明授权

US07385422B2 Tri-state output logic with zero quiescent current by one input control 失效
标题翻译：具有零静态电流的三态输出逻辑由一个输入控制
公开(公告)号：US07385422B2
公开(公告)日：2008-06-10
申请号：US11217341
申请日：2005-09-02
申请人： Shui-Mu Lin , Chien-Sheng Chen , Nien-Hui Kung , Der-Jiunn Wang , Jing-Meng Liu , Wei-Hsin Wei
发明人： Shui-Mu Lin , Chien-Sheng Chen , Nien-Hui Kung , Der-Jiunn Wang , Jing-Meng Liu , Wei-Hsin Wei
IPC分类号： H03K19/02
CPC分类号： G06F1/26
摘要： A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.
摘要翻译：提出了根据输入节点的高，低或浮动产生三态逻辑输出的电压产生电路。本电压发生电路包括：产生多个脉冲的脉冲发生电路; 一个电压选择电路，具有耦合在公共源极上的一对NMOS晶体管，NMOS晶体管的每个漏极分别耦合到电流源，NMOS晶体管的两个栅极耦合到输入节点，并且NMOS晶体管的成对漏极产生一对电压输出; 多个触发器，其耦合到NMOS晶体管的漏极以根据脉冲锁定NMOS晶体管的电压输出; 内部电压产生单元耦合到输入节点以提供浮动电压电平; 以及由用于控制电压选择电路的正常操作的脉冲控制的多个开关以及内部电压产生单元与输入节点之间的导通。

56. 发明申请

US20090015543A1 Frame-shifted backlight-scaled display system and frame-shifted backlight scaling method 审中-公开
标题翻译：帧移背光显示系统和帧移背光缩放方法
公开(公告)号：US20090015543A1
公开(公告)日：2009-01-15
申请号：US12216720
申请日：2008-07-10
申请人： Wei-Hsin Wei , Jing-Meng Liu
发明人： Wei-Hsin Wei , Jing-Meng Liu
IPC分类号： G09G3/36
CPC分类号： G09G3/3406 , G09G2320/0646 , G09G2330/021 , G09G2340/16
摘要： In a backlight scaling method and system, the pixel values of a first frame are counted to obtain a first histogram of this frame simultaneously when the first frame is inputted to the data driver ICs, and a first backlight luminance generated according to the first histogram is applied to the backlight driver for the backlight scaling for a second frame when the derived second frame is inputted to the data driver after the pixel values of the second frame is recalculated by the first backlight luminance. In the same way, when the derived second frame is inputted to the data driver, the original pixel values of the second frame are counted to obtain a second histogram of this frame and to generate a second backlight luminance for the third frame, and so on. Because the backlight luminance for each frame is generated according to the histogram of the previous frame, only small amount of pixel buffers for the processing is required.
摘要翻译：在背光缩放方法和系统中，当第一帧被输入到数据驱动器IC时，对第一帧的像素值进行计数以同时获得该帧的第一直方图，并且根据第一直方图生成的第一背光亮度为当在第二帧的像素值被第一背光亮度重新计算之后，当所导出的第二帧被输入到数据驱动器时，应用于用于第二帧的背光缩放的背光驱动器。以相同的方式，当将导出的第二帧输入到数据驱动器时，对第二帧的原始像素值进行计数以获得该帧的第二直方图，并产生第三帧的第二背光亮度，等等。由于根据前一帧的直方图产生每帧的背光亮度，因此仅需要少量用于处理的像素缓冲器。

57. 发明申请

US20160218617A1 POWER SUPPLY CIRCUIT WITH PFC FUNCTION, AND AUTOMATIC GAIN CONTROL CIRCUIT THEREFOR AND CONTROL METHOD THEREOF 审中-公开
公开(公告)号：US20160218617A1
公开(公告)日：2016-07-28
申请号：US15092014
申请日：2016-04-06
申请人： Chia-Wei Liao , Jing-Meng Liu
发明人： Chia-Wei Liao , Jing-Meng Liu
IPC分类号： H02M1/42 , H02M1/08 , G05F3/26
CPC分类号： H02M1/42 , G05F3/262 , H02M1/08 , H02M1/126 , H02M1/4208 , H02M2001/0009 , Y02B70/126
摘要： The present invention discloses a power supply circuit with power factor correction (PFC) function, and an automatic gain control circuit therefor and a control method thereof. The power supply circuit includes the automatic gain control circuit and a load driver circuit. The automatic gain control circuit converts an input voltage to a regulation voltage, and the load driver circuit generates an output current according to the regulation voltage. The automatic gain control circuit automatically adjust the regulation voltage such that the regulation voltage has a substantially fixed amplitude or fixed average value under different input voltages of different specifications, and the output current provided by the load driver circuit varies in phase with the input voltage to provide a PFC function.

58. 发明授权

US08884537B2 Active bleeder circuit triggering TRIAC in all phase and light emitting device power supply circuit and TRIAC control method using the active bleeder circuit 有权
标题翻译：在所有相和发光器件电源电路中触发TRIAC的有源泄放电路和使用主动泄放电路的TRIAC控制方法
公开(公告)号：US08884537B2
公开(公告)日：2014-11-11
申请号：US13728541
申请日：2012-12-27
申请人： Chia-Wei Liao , Leng-Nien Hsiu , Pei-Yuan Chen , Roland Van Roy , Jing-Meng Liu
发明人： Chia-Wei Liao , Leng-Nien Hsiu , Pei-Yuan Chen , Roland Van Roy , Jing-Meng Liu
IPC分类号： H05B37/02 , H05B39/02 , H05B39/04 , H05B41/36 , G05F3/02 , G05F1/455 , H05B33/08 , G05F1/10
CPC分类号： G05F1/455 , G05F1/10 , G05F3/02 , H05B33/0815 , H05B37/02 , Y02B20/346
摘要： The present invention discloses an active bleeder circuit capable of triggering a tri-electrode AC switch (TRIAC) circuit in all phase. The active bleeder circuit receives a rectified signal having an OFF phase and an ON phase. The active bleeder includes: a detection circuit for generating a detection signal according to the rectified signal and accumulating the detection signal in the OFF phase of the rectified signal; and a current sinker circuit coupled to the detection circuit, for generates a latching current to trigger the TRIAC circuit by operating a switch when the detection signal exceeds a predetermined level. The present invention also discloses a light emitting device power supply circuit and a TRIAC control method using the active bleeder circuit.
摘要翻译：本发明公开了一种能够全相触发三电极交流开关（TRIAC）电路的有源泄放电路。有源泄放电路接收具有OFF相位和ON相位的整流信号。有源放电器包括：检测电路，用于根据整流信号产生检测信号，并将检测信号累积在整流信号的OFF相位; 以及耦合到检测电路的电流沉降电路，用于当检测信号超过预定电平时，通过操作开关产生触发TRIAC电路的锁存电流。本发明还公开了一种使用有源泄放电路的发光器件电源电路和TRIAC控制方法。

59. 发明授权

US08710755B2 Light emitting device power supply circuit, and light emitting device driver circuit and control method thereof 有权
标题翻译：发光装置电源电路及发光装置驱动电路及其控制方法
公开(公告)号：US08710755B2
公开(公告)日：2014-04-29
申请号：US13421733
申请日：2012-03-15
申请人： Pei-Yuan Chen , Chia-Wei Liao , Jing-Meng Liu , Leng-Nien Hsiu
发明人： Pei-Yuan Chen , Chia-Wei Liao , Jing-Meng Liu , Leng-Nien Hsiu
IPC分类号： H05B37/02
CPC分类号： H05B33/0815
摘要： The present invention discloses a light emitting device power supply circuit, a light emitting device driver circuit and a control method thereof. The light emitting device driver circuit is coupled to a tri-electrode AC switch (TRIAC) dimmer circuit, and it controls the brightness of a light emitting device circuit according a rectified dimming signal. The light emitting device driver circuit includes a power stage circuit and a light emitting device control circuit. The light emitting device control circuit generates a switch control signal. The power stage circuit operates at least one power switch thereof according to the switch control signal to generate a latching current for firing the TRIAC dimmer circuit, and the latching current is inputted to the light emitting device circuit.
摘要翻译：本发明公开了一种发光装置电源电路，发光装置驱动电路及其控制方法。发光器件驱动电路耦合到三极交流开关（TRIAC）调光电路，并根据整流调光信号控制发光器件电路的亮度。发光器件驱动电路包括功率级电路和发光器件控制电路。发光装置控制电路产生开关控制信号。功率级电路根据开关控制信号操作其至少一个电源开关，以产生用于触发TRIAC调光电路的锁存电流，并且将锁存电流输入到发光器件电路。

60. 发明授权

US08531491B2 Control circuit for an organic light emitting diode panel 失效
标题翻译：有机发光二极管面板的控制电路
公开(公告)号：US08531491B2
公开(公告)日：2013-09-10
申请号：US12782253
申请日：2010-05-18
申请人： Jing-Meng Liu
发明人： Jing-Meng Liu
IPC分类号： G09G5/10 , H03K5/22
CPC分类号： H05B33/0896 , H05B33/0827
摘要： The present invention discloses a current-matching circuit including a hierarchical tree structure having two or more levels, each of which includes multiple matching devices, wherein each matching device at a preceding level corresponds to a predetermined number of matching devices at a next level. Respective matching devices at a last level control currents in respective current channels; the channels of the same group are matched with one another in current.
摘要翻译：本发明公开了一种电流匹配电路，其包括具有两个或更多个层次的分层树结构，每个级别包括多个匹配装置，其中前一级的每个匹配装置对应于下一级的预定数量的匹配装置。最后一级的各匹配装置控制各个电流通道中的电流; 同一组的通道在当前相互匹配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式