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    • 1. 发明授权
    • Tri-state output logic with zero quiescent current by one input control
    • 具有零静态电流的三态输出逻辑由一个输入控制
    • US07385422B2
    • 2008-06-10
    • US11217341
    • 2005-09-02
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • H03K19/02
    • G06F1/26
    • A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.
    • 提出了根据输入节点的高,低或浮动产生三态逻辑输出的电压产生电路。 本电压发生电路包括:产生多个脉冲的脉冲发生电路; 一个电压选择电路,具有耦合在公共源极上的一对NMOS晶体管,NMOS晶体管的每个漏极分别耦合到电流源,NMOS晶体管的两个栅极耦合到输入节点,并且NMOS晶体管的成对漏极 产生一对电压输出; 多个触发器,其耦合到NMOS晶体管的漏极以根据脉冲锁定NMOS晶体管的电压输出; 内部电压产生单元耦合到输入节点以提供浮动电压电平; 以及由用于控制电压选择电路的正常操作的脉冲控制的多个开关以及内部电压产生单元与输入节点之间的导通。
    • 2. 发明申请
    • Tri-state output logic with zero quiescent current by one input control
    • 具有零静态电流的三态输出逻辑由一个输入控制
    • US20060279331A1
    • 2006-12-14
    • US11217341
    • 2005-09-02
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • H03K19/00
    • G06F1/26
    • A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.
    • 提出了根据输入节点的高,低或浮动产生三态逻辑输出的电压产生电路。 本电压发生电路包括:产生多个脉冲的脉冲发生电路; 一个电压选择电路,具有耦合在公共源极上的一对NMOS晶体管,NMOS晶体管的每个漏极分别耦合到电流源,NMOS晶体管的两个栅极耦合到输入节点,并且NMOS晶体管的成对漏极 产生一对电压输出; 多个触发器,其耦合到NMOS晶体管的漏极以根据脉冲锁定NMOS晶体管的电压输出; 内部电压产生单元耦合到输入节点以提供浮动电压电平; 以及由用于控制电压选择电路的正常操作的脉冲控制的多个开关以及内部电压产生单元与输入节点之间的导通。