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1. 发明授权

US07768033B2 Single-chip common-drain JFET device and its applications 有权
公开(公告)号：US07768033B2
公开(公告)日：2010-08-03
申请号：US12385720
申请日：2009-04-17
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/098 , H01L27/0744 , H01L29/7722 , H01L29/8083
摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

2. 发明授权

US07759695B2 Single-chip common-drain JFET device and its applications 失效
标题翻译：单片共漏极JFET器件及其应用
公开(公告)号：US07759695B2
公开(公告)日：2010-07-20
申请号：US12385717
申请日：2009-04-17
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/098 , H01L27/0744 , H01L29/7722 , H01L29/8083
摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
摘要翻译：单芯片公共漏极JFET器件包括漏极，两个栅极和两个源极，使得与其形成两个公共漏极JFET。由于在单个芯片内合并的两个JFET，其间不需要引线接合连接，因此没有由接合线引起的寄生电感和电阻，因此提高性能并降低封装成本。单片式公共漏极JFET器件可以应用于降压转换器，升压转换器，反相转换器，开关和两级DC-DC转换器，以提高其性能和效率。还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

3. 发明授权

US07535032B2 Single-chip common-drain JFET device and its applications 失效
标题翻译：单片共漏极JFET器件及其应用
公开(公告)号：US07535032B2
公开(公告)日：2009-05-19
申请号：US11165028
申请日：2005-06-24
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/098 , H01L27/0744 , H01L29/7722 , H01L29/8083
摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
摘要翻译：单芯片公共漏极JFET器件包括漏极，两个栅极和两个源极，使得与其形成两个公共漏极JFET。由于在单个芯片内合并的两个JFET，其间不需要引线接合连接，因此没有由接合线引起的寄生电感和电阻，因此提高性能并降低封装成本。单片式公共漏极JFET器件可以应用于降压转换器，升压转换器，反相转换器，开关和两级DC-DC转换器，以提高其性能和效率。还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

4. 发明申请

US20070176636A1 Power supply circuit and control method thereof 有权
标题翻译：电源电路及其控制方法
公开(公告)号：US20070176636A1
公开(公告)日：2007-08-02
申请号：US11650525
申请日：2007-01-08
申请人： Jing-Meng Liu , Hung-Der Su
发明人： Jing-Meng Liu , Hung-Der Su
IPC分类号： H03K19/0175
CPC分类号： H02M3/156
摘要： A power supply circuit and a control method are provided, in which the original enable pad and output pad, or the enable pad and feedback pad are used to trim the output voltage of the power supply circuit without extra trim pads.
摘要翻译：提供了电源电路和控制方法，其中原始使能焊盘和输出焊盘或使能焊盘和反馈焊盘用于修剪电源电路的输出电压而无需额外的修整焊盘。

5. 发明申请

US20060214648A1 Control apparatus and method for a boost-inverting converter 有权
标题翻译：升压反相转换器的控制装置和方法
公开(公告)号：US20060214648A1
公开(公告)日：2006-09-28
申请号：US11388158
申请日：2006-03-24
申请人： Jing-Meng Liu , Chung-Lung Pai , Hung-Der Su , Wei-Hsin Wei
发明人： Jing-Meng Liu , Chung-Lung Pai , Hung-Der Su , Wei-Hsin Wei
IPC分类号： G05F1/00
CPC分类号： H02M3/157 , H02M3/1588 , Y02B70/1466
摘要： A plurality of switches, an inductor and two capacitors are configured to be a boost-inverting converter. To operate the converter in a boost-inverting mode, a control apparatus and method switch the switches such that the inductor is energized in a first phase, the first capacitor is discharged to produce an inverting voltage in a second phase, and the second capacitor is charged to produce a boost voltage in a third phase. Therefore, the boost-inverting converter has lower peak inductor current and less power loss, and the limitation to the switch design for the boost-inverting converter is relaxed.
摘要翻译：多个开关，电感器和两个电容器被配置为升压反相转换器。为了在升压反转模式下操作转换器，控制装置和方法切换开关使得电感器在第一相中通电，第一电容器被放电以在第二相中产生反相电压，并且第二电容器充电以在第三相中产生升压电压。因此，升压反相转换器具有较低的峰值电感电流和较小的功率损耗，并且对升压反相转换器的开关设计的限制放宽。

6. 发明申请

US20050285158A1 Single-chip common-drain JFET device and its applications 失效
标题翻译：单片共漏极JFET器件及其应用
公开(公告)号：US20050285158A1
公开(公告)日：2005-12-29
申请号：US11165028
申请日：2005-06-24
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H01L27/07 , H01L27/098 , H01L29/772 , H01L29/80 , H01L29/808
CPC分类号： H01L27/098 , H01L27/0744 , H01L29/7722 , H01L29/8083
摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
摘要翻译：单芯片公共漏极JFET器件包括漏极，两个栅极和两个源极，使得与其形成两个公共漏极JFET。由于在单个芯片内合并的两个JFET，其间不需要引线接合连接，因此没有由接合线引起的寄生电感和电阻，因此提高性能并降低封装成本。单片式公共漏极JFET器件可以应用于降压转换器，升压转换器，反相转换器，开关和两级DC-DC转换器，以提高其性能和效率。还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

7. 发明授权

US07838902B2 Single-chip common-drain JFET device and its applications 失效
公开(公告)号：US07838902B2
公开(公告)日：2010-11-23
申请号：US12385721
申请日：2009-04-17
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/098 , H01L27/0744 , H01L29/7722 , H01L29/8083
摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

8. 发明授权

US07382172B2 Level shift circuit and method for the same 有权
标题翻译：电平移位电路及方法相同
公开(公告)号：US07382172B2
公开(公告)日：2008-06-03
申请号：US11497587
申请日：2006-08-02
申请人： Pao-Chuan Lin , Hung-Der Su , An-Tung Chen , Jing-Meng Liu
发明人： Pao-Chuan Lin , Hung-Der Su , An-Tung Chen , Jing-Meng Liu
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , H03K3/012
摘要： The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operational voltage and providing current to the output of the level shift means to speed up output level switching. The circuit preferably further comprises a power consumption control circuit for stopping excess power consumption when the output of the level shift means has substantially accomplished level switching.
摘要翻译：本发明公开了一种电平移位电路，包括：电平移位装置，用于接收第一工作电压的输入并产生第二工作电压的输出; 以及与第二工作电压源连接并将电流提供给电平移位装置的输出的电流路径，以加速输出电平切换。电路优选地还包括功率消耗控制电路，用于在电平移位装置的输出基本上实现电平切换时停止多余的功率消耗。

9. 发明授权

US07327124B2 Control apparatus and method for a boost-inverting converter 有权
标题翻译：升压反相转换器的控制装置和方法
公开(公告)号：US07327124B2
公开(公告)日：2008-02-05
申请号：US11388158
申请日：2006-03-24
申请人： Jing-Meng Liu , Chung-Lung Pai , Hung-Der Su , Wei-Hsin Wei
发明人： Jing-Meng Liu , Chung-Lung Pai , Hung-Der Su , Wei-Hsin Wei
IPC分类号： G05F1/577
CPC分类号： H02M3/157 , H02M3/1588 , Y02B70/1466
摘要： A plurality of switches, an inductor and two capacitors are configured to be a boost-inverting converter. To operate the converter in a boost-inverting mode, a control apparatus and method switch the switches such that the inductor is energized in a first phase, the first capacitor is discharged to produce an inverting voltage in a second phase, and the capacitor Cout1 is discharged to produce the inverting voltage and the second capacitor is charged to produce a boost voltage in a third phase. Therefore, the boost-inverting converter has lower peak inductor current and less power loss, and the limitation to the switch design for the boost-inverting converter is relaxed.
摘要翻译：多个开关，电感器和两个电容器被配置为升压反相转换器。为了在升压反转模式下操作转换器，控制装置和方法切换开关使得电感器在第一相中通电，第一电容器被放电以产生第二相的反相电压，并且电容器Cout 1 被放电以产生反相电压，并且第二电容器被充电以在第三相中产生升压电压。因此，升压反相转换器具有较低的峰值电感电流和较小的功率损耗，并且对升压反相转换器的开关设计的限制放宽。

10. 发明申请

US20060109046A1 Method for determining switching state of a transistor-based switching device 有权
标题翻译：用于确定基于晶体管的开关器件的开关状态的方法
公开(公告)号：US20060109046A1
公开(公告)日：2006-05-25
申请号：US11108742
申请日：2005-04-19
申请人： Chun-Yen Huang , Hung-Der Su , Jing-Meng Liu , Chung-Lung Pai , Shih-Hui Chen , Yang-Ping Hung
发明人： Chun-Yen Huang , Hung-Der Su , Jing-Meng Liu , Chung-Lung Pai , Shih-Hui Chen , Yang-Ping Hung
IPC分类号： H03K17/00
CPC分类号： H03K17/0822 , H03K3/00 , H03K17/00 , H03K17/18 , H03K17/6871
摘要： A method, which is for determining switching state of a transistor-based switching device that includes a set of transistors, includes the steps of: applying a bias voltage to a transistor having a fastest response so as to dispose the transistors in the set in a desired transistor state; detecting a voltage level at a transistor having a slowest response to the bias voltage; and comparing the detected voltage level with a predetermined threshold voltage level in order to determine the switching state of the switching device. A transistor-based switching device is also disclosed.
摘要翻译：一种用于确定包括一组晶体管的基于晶体管的开关器件的开关状态的方法包括以下步骤：将偏置电压施加到具有最快响应的晶体管，以将晶体管置于该组中的晶体管中所需晶体管状态; 检测对所述偏置电压具有最慢响应的晶体管的电压电平; 以及将检测到的电压电平与预定阈值电压电平进行比较，以便确定开关器件的开关状态。还公开了一种基于晶体管的开关器件。

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