专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06393550B1 Method and apparatus for pipeline streamlining where resources are immediate or certainly retired 失效
标题翻译：用于管道精简的方法和装置，其中资源是立即的或肯定退休的
公开(公告)号：US06393550B1
公开(公告)日：2002-05-21
申请号：US08532225
申请日：1995-09-19
申请人： Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F930
CPC分类号： G06F9/30167 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： Maximum throughput or “back-to-back” scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.
摘要翻译：通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。这两个操作通过多种机制来实现。用于确定源操作数的可用性以及因此用于调度到可用执行单元的依赖指令的准备状态的一种机制依赖于在源操作数为退休或即时值时在分配期间早期设置源有效位。这允许保留站的就绪逻辑开始调度发送指令。

52. 发明授权

US5809325A Circuit and method for scheduling instructions by predicting future availability of resources required for execution 失效
公开(公告)号：US5809325A
公开(公告)日：1998-09-15
申请号：US676528
申请日：1996-07-09
申请人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
发明人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F9/3889 , G06F9/3891
摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

53. 发明授权

US5842036A Circuit and method for scheduling instructions by predicting future availability of resources required for execution 失效
公开(公告)号：US5842036A
公开(公告)日：1998-11-24
申请号：US954444
申请日：1997-10-20
申请人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
发明人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F9/3889 , G06F9/3891
摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

54. 发明授权

US5555432A Circuit and method for scheduling instructions by predicting future availability of resources required for execution 失效
标题翻译：通过预测执行所需资源的未来可用性来调度指令的电路和方法
公开(公告)号：US5555432A
公开(公告)日：1996-09-10
申请号：US293388
申请日：1994-08-19
申请人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
发明人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F9/3889 , G06F9/3891
摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.
摘要翻译：公开了一种包括执行单元，存储单元和调度器的乱序执行处理器。存储单元存储等待执行所需资源的可用性的指令。调度器周期性地确定执行每个指令所需的资源是否可用，如果是，则将该指令分派到执行单元。执行单元在实际可用的硬件资源之前指示诸如功能单元和写回端口的硬件资源的未来可用性数个时钟周期。调度器基于硬件资源的未来可用性的指示来确定执行指令所需的资源的可用性，并且分派用于执行的指令。无序执行处理器还包括在实际完成执行之前确定源指令执行的多个时钟周期的未来完成的装置。调度器调度执行需要对操作数的这种源指令之一的执行结果的数据相关指令。一旦源指令的执行结果可用，旁路多路复用器将执行结果旁路到分派的数据相关指令中。旁路复用器将具有完全组合的操作数的数据相关指令发送到执行单元以供执行。

55. 发明授权

US5553256A Apparatus for pipeline streamlining where resources are immediate or certainly retired 失效
标题翻译：用于管道精简的设备，其中资源立即或肯定退休
公开(公告)号：US5553256A
公开(公告)日：1996-09-03
申请号：US464571
申请日：1995-06-05
申请人： Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F9/38 , G06F9/06
CPC分类号： G06F9/30167 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.
摘要翻译：通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。这两个操作通过多种机制来实现。用于确定源操作数的可用性以及因此用于调度到可用执行单元的依赖指令的准备状态的一种机制依赖于在源操作数为退休或即时值时在分配期间早期设置源有效位。这允许保留站的就绪逻辑开始调度发送指令。

56. 发明授权

US5604877A Method and apparatus for resolving return from subroutine instructions in a computer processor 失效
标题翻译：用于解决计算机处理器中子程序指令返回的方法和装置
公开(公告)号：US5604877A
公开(公告)日：1997-02-18
申请号：US176065
申请日：1994-01-04
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4426
摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.
摘要翻译：公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。该方法和设备分四个阶段解析子程序指令。第一阶段预测指令流中的调用子程序指令和子程序返回指令。当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。第三阶段执行从子程序返回指令，使得预测得到验证。最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

57. 发明授权

US09594648B2 Controlling non-redundant execution in a redundant multithreading (RMT) processor 有权
标题翻译：控制冗余多线程（RMT）处理器中的非冗余执行
公开(公告)号：US09594648B2
公开(公告)日：2017-03-14
申请号：US12317802
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr
IPC分类号： G06F9/38 , G06F11/16 , G06F9/30
CPC分类号： G06F11/1683 , G06F9/30189 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F9/3891 , G06F11/1641 , G06F11/1658
摘要： In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于控制冗余执行的方法，使得如果出现异常事件，则停止冗余执行，在其中一个线程中执行非冗余执行，直到异常事件被解析为止线程的状态被同步，并且继续冗余执行。描述和要求保护其他实施例。

58. 发明授权

US09141461B2 Machine check architecture execution environment for non-microcoded processor 有权
标题翻译：非微处理器的机器检查体系结构执行环境
公开(公告)号：US09141461B2
公开(公告)日：2015-09-22
申请号：US13924585
申请日：2013-06-23
申请人： Willam C. Rash , Scott D. Hanh , Glenn J. Hinton
发明人： Willam C. Rash , Scott D. Hanh , Glenn J. Hinton
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/1415 , G06F11/142 , G06F11/1443 , G06F2201/815
摘要： A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.
摘要翻译：一种用于实现机器检查架构环境的方法的技术。本公开的方法包括获得错误的发生。错误的发生导致非微编码处理设备进入错误监视状态。该方法使用专用存储器部分处理错误，用于错误监视状态，而非微编码处理设备处于错误监视状态。错误监控状态专用于错误处理。该方法进一步确定与错误相关联的信息。与错误相关联的信息是预定义的格式。

59. 发明申请

US20130268728A1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES 有权
标题翻译：用于实现具有不同操作模式的多级记忆层次的装置和方法
公开(公告)号：US20130268728A1
公开(公告)日：2013-10-10
申请号：US13994731
申请日：2011-09-30
申请人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
发明人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0246 , G06F12/0806 , G06F12/0808 , G06F12/0815 , G06F12/0888 , G06F12/0893 , G06F2212/205 , G06F2212/283 , G06F2212/6046 , G06F2212/621 , G06F2212/7201 , G11C7/1045 , G11C7/1072 , G11C13/0004 , G11C14/0045
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
摘要翻译：描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。这些更高性能的存储器件被称为“接近存储器”。在一个实施例中，“近存储器”被配置为以多种不同的操作模式操作，包括（但不限于）其中近端存储器作为远存储器的存储器高速缓存操作的第一模式，以及第二模式其中所述近存储器被分配有系统地址空间的第一地址范围，所述远存储器被分配了所述系统地址空间的第二地址范围，其中所述第一范围和第二范围表示整个系统地址空间。

60. 再颁专利

USRE44494E1 Processor having execution core sections operating at different clock rates 有权
公开(公告)号：USRE44494E1
公开(公告)日：2013-09-10
申请号：US10996328
申请日：2004-11-24
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F1/00 , G06F1/04 , G06F15/00 , G06F15/76 , G06F9/00
CPC分类号： G06F1/02 , G06F1/06 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式