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1. 发明授权

US5604877A Method and apparatus for resolving return from subroutine instructions in a computer processor 失效
标题翻译：用于解决计算机处理器中子程序指令返回的方法和装置
公开(公告)号：US5604877A
公开(公告)日：1997-02-18
申请号：US176065
申请日：1994-01-04
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4426
摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.
摘要翻译：公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。该方法和设备分四个阶段解析子程序指令。第一阶段预测指令流中的调用子程序指令和子程序返回指令。当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。第三阶段执行从子程序返回指令，使得预测得到验证。最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

2. 发明授权

US5574871A Method and apparatus for implementing a set-associative branch target buffer 失效
公开(公告)号：US5574871A
公开(公告)日：1996-11-12
申请号：US177155
申请日：1994-01-04
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

3. 发明授权

US5812839A Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit 失效
标题翻译：双预测分支系统具有分支恢复过程的两个步骤，仅在错误预测分支是无序单元中最旧的指令时激活
公开(公告)号：US5812839A
公开(公告)日：1998-09-22
申请号：US851141
申请日：1997-05-05
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844 , G06F9/3863 , G06F9/3885
摘要： A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.
摘要翻译：公开了一种用于流水线处理器的四级分支指令解析系统。分支指令解析系统的第一阶段预测指令流内分支指令的存在和结果，使得指令获取单元可以连续地获取指令。第二阶段解码所有提取的指令。如果解码级确定由第一级预测的分支指令不是分支指令，则解码级别刷新流水线并以校正的地址重新启动处理器。解码阶段验证分支预测阶段所做的所有分支预测。最后，解码阶段对分支预测阶段未预测的分支进行分支预测。第三阶段执行所有分支指令以确定最终分支结果和最终分支目标地址。分支执行阶段将最终分支结果和最终分支目标地址与预测的分支结果和预测分支目标地址进行比较，以确定处理器是否必须冲洗微处理器流水线的前端并以修正的地址重新启动。最终的分支解决阶段退出所有分支指令。退休阶段确保在错误预测的分支之后提取的任何指令不会被永久保留。

4. 发明授权

US5768576A Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor 失效
标题翻译：用于预测和处理计算机处理器中的子程序指令的解析返回的方法和装置
公开(公告)号：US5768576A
公开(公告)日：1998-06-16
申请号：US739743
申请日：1996-10-29
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4426
摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.
摘要翻译：公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。该方法和设备分四个阶段解析子程序指令。第一阶段预测指令流中的调用子程序指令和子程序返回指令。当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。第三阶段执行从子程序返回指令，使得预测得到验证。最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

5. 发明授权

US5903751A Method and apparatus for implementing a branch target buffer in CISC processor 失效
标题翻译：在CISC处理器中实现分支目标缓冲器的方法和装置
公开(公告)号：US5903751A
公开(公告)日：1999-05-11
申请号：US931807
申请日：1997-09-16
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.
摘要翻译：公开了一种使用计算机指令流预测分支指令的计算机处理器中的分支目标缓冲器电路。分支目标缓冲器电路使用分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。存储在分支目标缓冲区高速缓存中的分支信息由每个分支指令的最后一个字节寻址。当计算机处理器中的指令获取单元获取指令块时，它向分支目标缓冲器电路发送指令指针。基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓存以查看正在获取的块中的任何指令是否是分支指令。当分支目标缓冲器电路在分支目标缓冲器高速缓存中找到即将到来的分支指令时，分支目标缓冲器电路通知指令获取单元关于即将到来的分支指令。

6. 发明授权

US5918046A Method and apparatus for a branch instruction pointer table 失效
标题翻译：分支指令指针表的方法和装置
公开(公告)号：US5918046A
公开(公告)日：1999-06-29
申请号：US783073
申请日：1997-01-15
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Subramanian Natarajan , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Subramanian Natarajan , Reynold V. D'Sa
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/322 , G06F9/3861
摘要： A buffer is used to store information about the branch instructions within a pipelined microprocessor that can speculatively execute instructions. When a branch instruction in the microprocessor is decoded, the address of the instruction immediately following the branch instruction (the Next Linear Instruction Pointer or NLIP) and some processor state information is written into a Branch Instruction Pointer Table. The branch instruction then proceeds down the microprocessor pipeline. Eventually, the branch instruction is executed. The resolved branch outcome for the branch instruction is compared with a predicted branch outcome. If the branch prediction was correct, the microprocessor continues execution along the current path. However, if the branch prediction was wrong then the execution unit flushes the front-end microprocessor pipeline and restores the microprocessor state information that was stored in the Branch IP Table. If the branch was mispredicted as not taken, the execution unit instructs an Instruction Fetch Unit to resume execution at a final branch target address. Alternatively, if the branch was mispredicted as taken when the branch should not have been taken, the execution unit instructs the Instruction Fetch Unit to resume execution at the Next Linear Instruction Pointer (NLIP) address stored in the Branch IP Table.
摘要翻译：缓冲器用于存储可以推测性地执行指令的流水线微处理器内关于分支指令的信息。当微处理器中的分支指令被解码时，紧跟在分支指令（下一个线性指令指针或NLIP）之后的指令的地址和一些处理器状态信息被写入分支指令指针表。然后分支指令继续沿着微处理器管线。最终执行分支指令。将分支指令的分解结果与预测的分支结果进行比较。如果分支预测是正确的，则微处理器沿着当前路径继续执行。然而，如果分支预测错误，则执行单元刷新前端微处理器流水线并恢复存储在分支IP表中的微处理器状态信息。如果分支被错误预测为未被执行，则执行单元指示指令获取单元在最终分支目标地址处恢复执行。或者，如果在不支持分支时分支被错误预测，则执行单元指示指令获取单元在存储在分支IP表中的下一个线性指令指针（NLIP）地址处继续执行。

7. 发明授权

US5687338A Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor 失效
标题翻译：用于维持用于在流水线处理器中进行重写的宏指令的方法和装置
公开(公告)号：US5687338A
公开(公告)日：1997-11-11
申请号：US511296
申请日：1995-08-04
申请人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Ashwani K. Gupta , Glenn J. Hinton , David B. Papworth
发明人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Ashwani K. Gupta , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3814 , G06F12/0897 , G06F9/3802 , G06F9/3808 , G06F9/3863
摘要： A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache for caching macro instructions to be fetched, and a victim cache for caching victims from the instruction cache. To ensure the availability of a macro instruction for refetching, the instruction memory (the instruction cache and victim cache together) always stores a macro instruction that may need to be refetched until the macro instruction is committed to architectural state. A marker micro instruction is inserted into the processor pipeline when an instruction cache line is victimized. The marker specifies an entry in the victim cache occupied by the victimized cache line. When the marker instruction is committed to architectural state, the victim cache entry specified by the marker is deallocated in the victim cache to permit storage of other instruction cache victims.
摘要翻译：提供了一种用于处理器中的指令重写的方法和装置。为了确保宏指令在处理器处理事件之后可用于重新获取指令，或者在分支错误预测之后确定正确的重新启动地址，指令存储器包括用于缓存要获取的宏指令的指令高速缓存，以及用于缓存受害者的受害缓存从指令缓存。为了确保可用的宏指令进行重写，指令存储器（指令高速缓存和受害器缓存在一起）总是存储可能需要重新引导的宏指令，直到宏指令提交到架构状态。当指令高速缓存线受害时，标记微指令被插入到处理器流水线中。标记指定受害缓存行占用的受害缓存中的条目。当标记指令被提交到架构状态时，标记指定的受害者缓存条目被释放在受害缓存中，以允许存储其他指令缓存受害者。

8. 发明授权

US5584037A Entry allocation in a circular buffer 失效
标题翻译：循环缓冲区中的条目分配
公开(公告)号：US5584037A
公开(公告)日：1996-12-10
申请号：US571377
申请日：1995-12-13
申请人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
发明人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
IPC分类号： G06F5/10 , G06F5/14 , G06F9/38 , G06F12/00
CPC分类号： G06F5/14 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.
摘要翻译：分配器为循环缓冲区分配条目。分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。分配器具有用于执行无序调度和推测执行的微处理器的应用。分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

9. 发明授权

US5564111A Method and apparatus for implementing a non-blocking translation lookaside buffer 失效
标题翻译：用于实现非阻塞转换后备缓冲器的方法和装置
公开(公告)号：US5564111A
公开(公告)日：1996-10-08
申请号：US315833
申请日：1994-09-30
申请人： Andrew F. Glew , Haitham Akkary , Robert P. Colwell , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman
发明人： Andrew F. Glew , Haitham Akkary , Robert P. Colwell , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman
IPC分类号： G06F9/38 , G06F11/00 , G06F12/10 , G06F11/34
CPC分类号： G06F9/3865 , G06F11/0751 , G06F12/1027 , G06F9/3842 , G06F2212/684
摘要： A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.
摘要翻译：描述了用于能够处理推测和乱序指令的微处理器中的非阻塞转换后备缓冲器。在检测到故障时，无论是在翻译后备缓冲器命中还是响应于翻译后备缓冲器未命中执行的页表行走期间，与故障指令相关联的信息都存储在翻译后备缓冲器内的故障寄存器内。所存储的信息包括指令的线性地址和识别指令年龄的信息。除了将信息存储在故障寄存器之外，信息的一部分被发送到微处理器的重排序缓冲器以便存储在故障指令中。在故障指令退出之前，翻译后备缓冲区继续处理进一步的指令。在每个指令退出后，重新排序缓冲器确定是否检测到该指令发生故障，如果是，则清除微处理器。然后，一个分支被带入微码。微代码访问存储在翻译后备缓冲区的故障寄存器内的线性地址和其他信息，并处理故障。系统被刷新，微代码仅对实际退出的故障指令执行。因此，基于错误预测的分支处理推测性指令时检测到的故障不会妨碍进一步的地址转换，并且不会导致系统被刷新。本文描述了方法和装置实现。

10. 发明授权

US6101597A Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor 失效
标题翻译：用于流水线处理器中依赖操作的最大吞吐量调度的方法和装置
公开(公告)号：US6101597A
公开(公告)日：2000-08-08
申请号：US176370
申请日：1993-12-30
申请人： Robert P. Colwell , Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Robert P. Colwell , Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3824 , G06F9/383
摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM). Before an instruction is executed and its result data written back, the storage location address of the result is provided to the CAM and associatively compared with the source operand addresses stored therein. A CAM match and its accompanying match bit indicate that the result of the instruction to be executed will provide a source operand to the dependent instruction waiting in the reservation station. Using a bypass mechanism, if the operand is computed after dispatch of the dependent instruction, then the source operand is provided directly from the execution unit computing the source operand to a source operand input of the execution unit executing the dependent instruction.
摘要翻译：通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。这两个操作通过多个机制来实现。用于确定源操作数的可用性以及因此用于发送到可用执行单元的依赖指令的准备的机制依赖于在操作数本身实际计算之前源操作数的可用性的预期确定执行另一条指令。指令的源操作数的存储地址存储在内容可寻址存储器（CAM）中。在执行指令并且其结果数据被写回之前，将结果的存储位置地址提供给CAM并与存储在其中的源操作数地址相关联地进行比较。 CAM匹配及其伴随的匹配位指示要执行的指令的结果将为在保留站等待的从属指令提供源操作数。使用旁路机制，如果在分派依赖指令之后计算操作数，则将操作数从执行单元直接提供到计算源操作数到执行依赖指令的执行单元的源操作数输入。

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