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51. 发明申请

US20100297825A1 Passive Components in the Back End of Integrated Circuits 有权
标题翻译：集成电路后端的无源元件
公开(公告)号：US20100297825A1
公开(公告)日：2010-11-25
申请号：US12849086
申请日：2010-08-03
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Olivier Plouchart , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Olivier Plouchart , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译：通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

52. 发明申请

US20100279483A1 LATERAL PASSIVE DEVICE HAVING DUAL ANNULAR ELECTRODES 有权
标题翻译：具有双重电极的侧向被动装置
公开(公告)号：US20100279483A1
公开(公告)日：2010-11-04
申请号：US12835283
申请日：2010-07-13
申请人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/329 , H01L21/04
CPC分类号： H01L29/8611 , H01L27/0814 , H01L29/417 , H01L29/868 , H01L29/872 , H01L29/93
摘要： A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed.
摘要翻译：公开了一种包括双环形电极的横向无源器件。环形电极形成阳极和阴极。环形电极允许将阳极和阴极串联电阻优化为固定装置区域的最低值。此外，对底板（衬底）的寄生电容大大降低。在一个实施例中，装置包括围绕形成在基板上的第二环形电极的第一环形电极，并且第二环形电极围绕绝缘体区域。还公开了相关方法。

53. 发明授权

US07808039B2 SOI transistor with merged lateral bipolar transistor 失效
标题翻译：具有合并横向双极晶体管的SOI晶体管
公开(公告)号：US07808039B2
公开(公告)日：2010-10-05
申请号：US12099879
申请日：2008-04-09
申请人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
发明人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
IPC分类号： H01L27/088
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/0722
摘要： A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.
摘要翻译：绝缘体上半导体晶体管器件包括源极区，漏极区，体区和源极横向双极晶体管。源区具有第一导电类型。体区具有第二导电类型并且位于源区和漏区之间。源极横向双极晶体管包括基极，集电极和发射极。硅化物区将基底连接到收集器。发射器是身体区域。集电体具有第二导电类型，基极是源极区，位于发射极和集电极之间。

54. 发明申请

US20100248432A1 METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT 有权
标题翻译：形成用于集成电路的高压P-N结和设计结构的方法
公开(公告)号：US20100248432A1
公开(公告)日：2010-09-30
申请号：US12795108
申请日：2010-06-07
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/84 , G06F17/50
CPC分类号： H01L29/93
摘要： Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.
摘要翻译：形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。反渗透定义了超突变p-n结。在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。

55. 发明授权

US07804119B2 Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit 失效
标题翻译：具有超陡P-N结的器件结构，形成超陡P-N结的方法，以及集成电路的设计结构
公开(公告)号：US07804119B2
公开(公告)日：2010-09-28
申请号：US12099316
申请日：2008-04-08
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L27/108
CPC分类号： H01L29/93
摘要： Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.
摘要翻译：具有超突变p-n结的器件结构，形成超突变p-n结的方法以及包含具有超突变p-n结的器件结构的集成电路的设计结构。通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。反渗透定义了超突变p-n结。在离子注入期间，在器件层的顶表面上承载的栅极结构作为硬掩模进行操作，以有助于限定超突变n结的横向边界。

56. 发明申请

US20100117237A1 Silicided Trench Contact to Buried Conductive Layer 失效
标题翻译：硅胶沟与埋地导电层接触
公开(公告)号：US20100117237A1
公开(公告)日：2010-05-13
申请号：US12269069
申请日：2008-11-12
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L23/52 , H01L21/02
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

57. 发明授权

US07476926B2 Eraseable nonvolatile memory with sidewall storage 有权
标题翻译：具有侧壁存储的可擦除非易失性存储器
公开(公告)号：US07476926B2
公开(公告)日：2009-01-13
申请号：US10905475
申请日：2005-01-06
申请人： Chung H. Lam , Jeffrey B. Johnson
发明人： Chung H. Lam , Jeffrey B. Johnson
IPC分类号： H01L29/76
CPC分类号： H01L29/66833 , G11C16/0475 , H01L21/28282 , H01L29/7923
摘要： A nonvolatile storage cell and an integrated circuit (IC) including the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride layer) in the layered spacer.
摘要翻译：非易失性存储单元和包括这些单元的集成电路（IC）。至少在单元格栅极的一个侧壁处形成分层间隔物（ONO）。每个分层隔离层处的源极/漏极扩散层叠在邻近的栅极上。电荷可以存储在分层间隔物中的层（嵌入的氮化物层）上。

58. 发明申请

US20080217742A1 TAILORED BIPOLAR TRANSISTOR DOPING PROFILE FOR IMPROVED RELIABILITY 审中-公开
标题翻译：定制的双极晶体管转换配置文件，以提高可靠性
公开(公告)号：US20080217742A1
公开(公告)日：2008-09-11
申请号：US11684142
申请日：2007-03-09
申请人： Jeffrey B. Johnson , Edward J. Nowak , Andreas D. Stricker , Benjamin T. Voegeli
发明人： Jeffrey B. Johnson , Edward J. Nowak , Andreas D. Stricker , Benjamin T. Voegeli
IPC分类号： H01L29/732
CPC分类号： H01L29/7322 , H01L29/0821 , H01L29/1004 , H01L29/66272
摘要： Bipolar transistor device structures that improve bipolar device reliability with little or no negative impact on device performance. In one embodiment, the bipolar device has a collector of first conductivity type material formed in a substrate, a base of a second conductivity type material including an extrinsic base layer and an intrinsic base layer, a raised emitter of a first conductivity type semiconductor material formed on the intrinsic base layer, and, a dielectric material layer separating the intrinsic base region and the raised emitter region, and, a thin “shunt” layer of dopant of second conductivity type material added to the region below the emitter dielectric layer. In a second embodiment, a selectively implanted collector (pedestal implant) is added to the vertical bipolar transistor device to enable a reduction in overall subcollector doping level to improve reliability without sacrificing device performance. These solutions add no additional masking steps and only one additional implantation step.
摘要翻译：双极晶体管器件结构，可以很好地改善双极器件的可靠性，对器件性能的影响很小或没有负面影响在一个实施例中，双极器件具有形成在衬底中的第一导电类型材料的集电体，包括非本征基极层和本征基极层的第二导电类型材料的基极，形成的第一导电类型半导体材料的凸起发射极在本征基极层上，以及分离本征基极区域和凸起的发射极区域的介电材料层，以及添加到发射极电介质层下方的区域的第二导电型材料的掺杂剂的薄的“分流”层。在第二实施例中，将选择性注入的集电极（基座注入）添加到垂直双极晶体管器件，以使整体子集电极掺杂水平降低，以提高可靠性而不牺牲器件性能。这些解决方案不会增加额外的掩蔽步骤和仅一个额外的植入步骤。

59. 发明授权

US6007628A Clamping fixture for a rotor blade shroud 失效
标题翻译：用于转子叶片护罩的夹具
公开(公告)号：US6007628A
公开(公告)日：1999-12-28
申请号：US994677
申请日：1997-12-19
申请人： Alan J. Ittleson , Bryan P. Dube , Jeffrey B. Johnson
发明人： Alan J. Ittleson , Bryan P. Dube , Jeffrey B. Johnson
IPC分类号： B23K9/173 , B05C13/00
CPC分类号： B23K9/173
摘要： A fixture 14 for use in applying a material to a face 16,18 of a rotor blade 10 is disclosed. Various construction details are developed which reduce rework of the rotor blade and facilitate application of the material are developed. In one embodiment, a pad 48 has a surface 50 which blocks the flow of molten material to the flow path surface 42 of the shroud 12 of the rotor blade and the fixture is supported and positioned from the rotor blade.
摘要翻译：公开了一种用于将材料施加到转子叶片10的表面16,18上的夹具14。开发了各种构造细节，其减少了转子叶片的返工，并且开发了材料的应用。在一个实施例中，垫48具有表面50，该表面阻挡熔融材料流到转子叶片的护罩12的流动路径表面42，并且夹具从转子叶片被支撑和定位。

60. 发明授权

US08872281B2 Silicided trench contact to buried conductive layer 有权
标题翻译：硅化沟槽接触埋入导电层
公开(公告)号：US08872281B2
公开(公告)日：2014-10-28
申请号：US13570737
申请日：2012-08-09
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Lie , James S. Nakos , Bradley A. Omer , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Lie , James S. Nakos , Bradley A. Omer , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L29/78 , H01L21/74 , H01L21/762
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

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