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51. 发明授权

US06410968B1 Semiconductor device with barrier layer 失效
标题翻译：具有阻挡层的半导体器件
公开(公告)号：US06410968B1
公开(公告)日：2002-06-25
申请号：US09653639
申请日：2000-08-31
申请人： Don Carl Powell , Garry Anthony Mercaldi , Ronald A. Weimer
发明人： Don Carl Powell , Garry Anthony Mercaldi , Ronald A. Weimer
IPC分类号： H01L31119
CPC分类号： H01L29/513 , H01L21/02123 , H01L21/02126 , H01L21/02211 , H01L21/02222 , H01L21/02263 , H01L21/02271 , H01L21/02337 , H01L21/28035 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3125 , H01L21/3143 , H01L21/3144 , H01L21/31612 , H01L21/3185 , H01L28/57 , H01L29/518 , H01L2924/19041
摘要： Methods and devices are disclosed utilizing a silicon-containing barrier layer. A method of forming a barrier layer on a semiconductor device is disclosed. A semiconductor device is provided. A silicon-containing material is deposited on the semiconductor device. The silicon-containing material is processed in a reactive ambient. The barrier layer can be made primarily oxide, primarily nitride or both by the reactive ambient selected. A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer. Other embodiments utilizing a barrier layer are disclosed.
摘要翻译：公开了利用含硅阻挡层的方法和装置。公开了一种在半导体器件上形成阻挡层的方法。提供半导体器件。含硅材料沉积在半导体器件上。含硅材料在反应性环境中进行处理。阻挡层可以主要由所选择的反应性环境制成主要是氧化物，主要是氮化物或二者。公开了一种半导体器件。半导体器件包括衬底，栅极氧化物，含硅势垒层和栅电极。栅极氧化物形成在衬底上。通过使前体层的硅原子与反应剂反应，在栅极氧化物上形成含硅势垒层。栅电极形成在含硅阻挡层的上方。公开了利用阻挡层的其它实施例。

52. 发明授权

US06348380B1 Use of dilute steam ambient for improvement of flash devices 失效
公开(公告)号：US06348380B1
公开(公告)日：2002-02-19
申请号：US09648699
申请日：2000-08-25
申请人： Ronald A. Weimer , Don C. Powell , John T. Moore , Jeff A. McKee
发明人： Ronald A. Weimer , Don C. Powell , John T. Moore , Jeff A. McKee
IPC分类号： H01L21336
CPC分类号： H01L29/517 , H01L21/28273 , H01L29/511
摘要： The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

53. 发明授权

US5759262A Method of forming hemispherical grained silicon 失效
标题翻译：形成半球形晶粒硅的方法
公开(公告)号：US5759262A
公开(公告)日：1998-06-02
申请号：US831181
申请日：1997-04-02
申请人： Ronald A. Weimer , Randhir P. S. Thakur , Avishai Kepten , Michael Sendler
发明人： Ronald A. Weimer , Randhir P. S. Thakur , Avishai Kepten , Michael Sendler
IPC分类号： C30B25/02 , C30B25/18 , H01L21/02 , C30B31/22
CPC分类号： C30B29/06 , C30B25/18 , H01L28/84 , H01L28/90 , Y10S438/964
摘要： A method of forming HSG is disclosed, in which a layer of starting material is formed on a wafer, the layer of starting material is seeded with a species and the seeded layer is annealed. The seeding and annealing steps can be performed under different conditions and can be varied independently of each other.
摘要翻译：公开了一种形成HSG的方法，其中在晶片上形成起始材料层，将起始材料层接种种类并使籽晶层退火。接种和退火步骤可以在不同条件下进行，并且可以彼此独立地变化。

54. 发明授权

US5688550A Method of forming polysilicon having a desired surface roughness 失效
标题翻译：形成具有所需表面粗糙度的多晶硅的方法
公开(公告)号：US5688550A
公开(公告)日：1997-11-18
申请号：US572968
申请日：1995-12-15
申请人： Ronald A. Weimer , Avishai Kepten , Michael Sendler
发明人： Ronald A. Weimer , Avishai Kepten , Michael Sendler
IPC分类号： C23C16/24 , C23C16/56 , H01L21/20 , H01L21/3205 , H01L21/66
CPC分类号： H01L22/26 , C23C16/24 , C23C16/56 , H01L21/3205 , H01L21/2022 , Y10S438/964
摘要： A method for reliably forming polysilicon of a desired surface roughness includes providing a layer of doped or undoped amorphous silicon on a substrate and heating said substrate while monitoring the emission of said substrate and comparing the monitored emission with an expected emission attributable to the heating regime employed. An increase in the monitored emission not attributable to the heating regime signals a transition of the layer of amorphous silicon to rough polysilicon. A decrease in the monitored emission not attributable to the heating regime signals a transition to smooth polysilicon. The increases and decreases in the monitored emission can be used to end the heating regime at the time at which the desired surface roughness of polysilicon is formed, or merely to passively monitor the process.
摘要翻译：可靠地形成期望表面粗糙度的多晶硅的方法包括在衬底上提供掺杂或未掺杂的非晶硅层并加热所述衬底，同时监测所述衬底的发射并将所监测的发射与可归因于所采用的加热方式的预期发射。不能归因于加热方式的监测发射的增加表明非晶硅层向粗多晶硅的转变。不受加热制度影响的监测排放的减少表明向多晶硅平滑过渡。监测发射的增加和减少可以用于在形成期望的多晶硅表面粗糙度的时候终止加热状态，或者仅仅被动地监视该过程。

55. 发明授权

US5634974A Method for forming hemispherical grained silicon 失效
标题翻译：形成半球形晶粒硅的方法
公开(公告)号：US5634974A
公开(公告)日：1997-06-03
申请号：US552828
申请日：1995-11-03
申请人： Ronald A. Weimer , Randhir P. S. Thakur , Avishai Kepten , Michael Sendler
发明人： Ronald A. Weimer , Randhir P. S. Thakur , Avishai Kepten , Michael Sendler
IPC分类号： C30B25/02 , C30B25/18 , H01L21/02 , C30B25/04
CPC分类号： C30B29/06 , C30B25/18 , H01L28/84 , H01L28/90 , Y10S438/964
摘要： A method of forming HSG is disclosed, in which a layer of starting material is formed on a wafer, the layer of starting material is seeded with a species and the seeded layer is annealed. The seeding and annealing steps can be performed under different conditions and can be varied independently of each other.
摘要翻译：公开了一种形成HSG的方法，其中在晶片上形成起始材料层，将起始材料层接种种类并使籽晶层退火。接种和退火步骤可以在不同条件下进行，并且可以彼此独立地变化。

56. 发明授权

US08384192B2 Methods for forming small-scale capacitor structures 有权
标题翻译：形成小型电容器结构的方法
公开(公告)号：US08384192B2
公开(公告)日：2013-02-26
申请号：US13047430
申请日：2011-03-14
申请人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
发明人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/3141 , H01L27/10852 , H01L28/60 , H01L28/84
摘要： The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.
摘要翻译：本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。第二导电层可以与介电层接触并具有不大于约的厚度。

57. 发明授权

US08119483B2 Methods of forming memory cells 有权
标题翻译：形成记忆细胞的方法
公开(公告)号：US08119483B2
公开(公告)日：2012-02-21
申请号：US13039600
申请日：2011-03-03
申请人： Ronald A. Weimer
发明人： Ronald A. Weimer
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.
摘要翻译：一些实施方案包括在形成非挥发性记忆体中使用聚硅氮烷的方法。存储器单元可以是多级单元（MLC）。聚硅氮烷可以通过热加工转化为氮化硅，二氧化硅或氮氧化硅，并暴露于含有氧和氮的一种或两种的环境中。所述方法可以包括使用聚硅氮烷形成非易失性存储单元的电荷捕获层。所述方法可以或另外包括使用聚硅氮烷形成非易失性存储单元的隔间介电材料。一些实施例包括形成NAND存储器阵列的存储单元的方法。

58. 发明申请

US20110254075A1 USE OF DILUTE STEAM AMBIENT FOR IMPROVEMENT OF FLASH DEVICES 有权
标题翻译：用于改进闪光装置的稀释蒸汽环境的使用
公开(公告)号：US20110254075A1
公开(公告)日：2011-10-20
申请号：US13168902
申请日：2011-06-24
申请人： Ronald A. Weimer , Don C. Powell , John T. Moore , Jeff A. McKee
发明人： Ronald A. Weimer , Don C. Powell , John T. Moore , Jeff A. McKee
IPC分类号： H01L29/788 , B82Y99/00
CPC分类号： H01L29/517 , H01L21/28273 , H01L29/511
摘要： A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.
摘要翻译：闪存集成电路及其制造方法。栅极堆叠包括直接与硅层接触的初始氧化物层，在其间界定氧化物 - 硅界面。另外的氧化物材料沿着氧化硅 - 硅界面基本均匀地形成。因此在界面处的多晶硅晶界被蚀刻后钝化。界面可以形成在隧道氧化物和浮动栅极之间，钝化晶界可以减少擦除变化。在稀释蒸汽氧化中，上储存电介质层中的氧化物增强。薄氧化物层用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

59. 发明授权

US07771537B2 Methods and systems for controlling temperature during microfeature workpiece processing, E.G. CVD deposition 有权
标题翻译：用于在微特征工件加工（例如CVD沉积）期间控制温度的方法和系统
公开(公告)号：US07771537B2
公开(公告)日：2010-08-10
申请号：US11418337
申请日：2006-05-04
申请人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
发明人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
IPC分类号： C23C16/00
CPC分类号： C23C16/00 , C23C16/46
摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
摘要翻译：本公开提供了用于控制温度的方法和系统。该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

60. 发明授权

US07651910B2 Methods of forming programmable memory devices 有权
标题翻译：形成可编程存储器件的方法
公开(公告)号：US07651910B2
公开(公告)日：2010-01-26
申请号：US10150623
申请日：2002-05-17
申请人： Kevin L. Beaman , Ronald A. Weimer
发明人： Kevin L. Beaman , Ronald A. Weimer
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28273 , H01L29/42324 , H01L29/511 , H01L29/518
摘要： The invention includes a method of forming a programmable memory device. A tunnel oxide is formed to be supported by a semiconductor substrate. A stack is formed over the tunnel oxide. The stack comprises a floating gate, dielectric mass and control gate. The stack has a top, and has opposing sidewalls extending downwardly from the top. The dielectric mass includes silicon nitride. Silicon nitride spacers are formed along sidewalls of the stack, and a silicon nitride cap is formed over a top of the stack. The silicon nitride within the dielectric mass, cap and/or sidewall spacers is formed from trichlorosilane and ammonia.
摘要翻译：本发明包括一种形成可编程存储器件的方法。隧道氧化物形成为被半导体衬底支撑。在隧道氧化物上形成堆叠。该堆叠包括浮动栅极，介电质量块和控制栅极。堆叠具有顶部，并且具有从顶部向下延伸的相对侧壁。介电质量包括氮化硅。氮化硅间隔物沿着堆叠的侧壁形成，并且在堆叠的顶部上形成氮化硅帽。介电体内的氮化硅，帽和/或侧壁间隔物由三氯硅烷和氨形成。

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