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51. 发明授权

US09047803B2 Display apparatus including bi-directional gate drive circuit 有权
标题翻译：显示装置包括双向栅极驱动电路
公开(公告)号：US09047803B2
公开(公告)日：2015-06-02
申请号：US13274939
申请日：2011-10-17
申请人： Jae-Hoon Lee , Chang-Ho Lee , Jun-Yong Song , Yu-Han Bae
发明人： Jae-Hoon Lee , Chang-Ho Lee , Jun-Yong Song , Yu-Han Bae
IPC分类号： G09G3/36 , G09G3/00 , G09G3/29
CPC分类号： G09G3/007 , G09G3/29 , G09G2300/0838 , G09G2300/0871 , G09G2310/0286 , G09G2310/0289
摘要： A gate drive circuit includes a plurality of driving stages. An n-th (‘n’ is a natural number) driving stage includes a pull-up part, a carry part, a first pull-down part, a first pull-up/down control part and a second pull-up/down control part. The first pull-up/down control part applies a first power signal of an ON voltage to a control terminal of the pull-up part in a forward direction mode, and applies the first power signal of a second OFF voltage to a control terminal of the pull-up part in a reverse direction mode. The second pull-up/down control part applies a second power signal of the second OFF voltage to the control terminal of the pull-up part in the forward direction mode, and applies the second power signal of the ON voltage to the control terminal of the pull-up part in the reverse direction mode.
摘要翻译：栅极驱动电路包括多个驱动级。第n（'n'是自然数）驱动级包括上拉部分，进位部分，第一下拉部分，第一上拉/下拉控制部分和第二上拉/下拉控制部分。第一上拉/下拉控制部分向前向模式向上拉部分的控制端施加导通电压的第一电源信号，并将第二OFF电压的第一电源信号施加到上拉部分处于反向模式。第二上拉/下拉控制部分将第二OFF电压的第二功率信号以正向模式施加到上拉部分的控制端，并将接通电压的第二功率信号施加到上拉部分处于反向模式。

52. 发明授权

US08629827B2 Display device and method of manufacturing the same 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US08629827B2
公开(公告)日：2014-01-14
申请号：US12762470
申请日：2010-04-19
申请人： Jae-Hoon Lee , Yong-Soon Lee , Young-Su Kim , Yu-Han Bae
发明人： Jae-Hoon Lee , Yong-Soon Lee , Young-Su Kim , Yu-Han Bae
IPC分类号： G06F3/038 , H01J9/00
CPC分类号： G09G3/3614 , G09G3/3607 , G09G2300/0426 , G09G2320/0209
摘要： A display device includes a display panel, a data driving part and a gate driving part. The display panel includes a first pixel row. The first pixel row includes a first pixel connected to an (n+1)-th gate line and an (m+1)-th data line (where ‘n’ and ‘m’ are natural numbers), and a second pixel connected to an n-th gate line and an (m+2)-th data line. The data driving part applies a data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line, and applies a data voltage having a second polarity with respect to the reference voltage to the (m+2)-th data line. The gate driving part sequentially applies a gate signal to the n-th gate line and the (n+1)-th gate line.
摘要翻译：显示装置包括显示面板，数据驱动部和门驱动部。显示面板包括第一像素行。第一像素行包括连接到第（n + 1）栅极线和第（m + 1）数据线（其中'n'和'm'是自然数）的第一像素，并且第二像素连接到第n个栅极线和第（m + 2）个数据线。数据驱动部分对第（m + 1）数据线施加相对于参考电压具有第一极性的数据电压，并将相对于参考电压具有第二极性的数据电压施加到第（m + 2）数据线。栅极驱动部分顺序地对第n条栅极线和第（n + 1）栅极线施加栅极信号。

53. 发明授权

US08416233B2 Display driver with charge pumping signals synchronized to different clocks for multiple modes 有权
公开(公告)号：US08416233B2
公开(公告)日：2013-04-09
申请号：US12590052
申请日：2009-11-02
申请人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
发明人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G5/006 , G09G3/3611 , G09G5/18
摘要： A display driver generates a respective charge pumping signal and respective driving signals synchronized to a respective same clock signal for each of the CPU and video interface modes. Because such respective signals are synchronized to a respective same clock signal, the noise superimposed on the driving signals applied on a display panel is regular and uniform across the whole display panel, for each of the CPU and video interface modes. Accordingly, affects of such regular noise are advantageously not noticeable to the human eye, for both the video and CPU interface modes of operation.

54. 发明授权

US08243058B2 Gate driving circuit and display device having the gate driving circuit 有权
标题翻译：栅极驱动电路和具有栅极驱动电路的显示装置
公开(公告)号：US08243058B2
公开(公告)日：2012-08-14
申请号：US12616604
申请日：2009-11-11
申请人： Jae-Hoon Lee , Jun-Yong Song , Hoi-Sik Moon , Yong-Soon Lee
发明人： Jae-Hoon Lee , Jun-Yong Song , Hoi-Sik Moon , Yong-Soon Lee
IPC分类号： G06F3/038
CPC分类号： G09G3/3677 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： A gate driving circuit includes a plurality of stages connected to each other. An m-th stage (‘m’ is a natural number) of the stages includes a pull-up part, a pull-down part, a first holding part and a second holding part. The pull-up part outputs a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage applied to a first output control part. The pull-down part pulls down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal. The first holding part holds a voltage applied to the first output control part as a second low voltage having a level lower than the first low voltage. The second holding part holds a low voltage of the m-th gate signal to the first low voltage.
摘要翻译：栅极驱动电路包括彼此连接的多个级。第m级（“m”是自然数）级包括上拉部分，下拉部分，第一保持部分和第二保持部分。响应于施加到第一输出控制部分的高电压，上拉部分输出作为第m门信号的高电压的时钟信号的高电压。下拉部分响应于第（m + 1）门信号的高电压将第m门信号的高电压下拉到第一低电压。第一保持部分将施加到第一输出控制部分的电压保持为具有低于第一低电压电平的第二低电压。第二保持部将第m栅极信号的低电压保持为第一低电压。

55. 发明申请

US20120161820A1 GATE DRIVE CIRCUIT, DISPLAY SUBSTRATE HAVING THE SAME AND METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE 有权
标题翻译：栅极驱动电路，具有该栅极的显示基板和制造显示基板的方法
公开(公告)号：US20120161820A1
公开(公告)日：2012-06-28
申请号：US13288893
申请日：2011-11-03
申请人： Bon-Yong Koo , Sung-Man Kim , Jae-Hoon Lee
发明人： Bon-Yong Koo , Sung-Man Kim , Jae-Hoon Lee
IPC分类号： H03K3/00 , H01L33/08
CPC分类号： H01L27/1259 , G09G3/3611 , H01L27/1255 , H01L29/41733
摘要： A gate drive circuit includes plural stages connected together one after each other. Each of the plural stages includes a circuit transistor, a capacitor part, a first connection part and a second connection part. The circuit transistor outputs the gate signal through a source electrode in response to a control signal applied through a gate electrode. The capacitor part includes a first electrode, a second electrode formed on the first electrode, and a third electrode formed on the second electrode. The first connection part electrically connects the gate electrode of the circuit transistor and the second electrode of the capacitor part. The second connection part electrically connects the source electrode of the circuit transistor and the first electrode of the capacitor part. Thus, an integrated size of a gate drive circuit may be decreased, and a reliability of a gate drive circuit may be enhanced.
摘要翻译：栅极驱动电路包括一个接一个地连接在一起的多个级。多级中的每一个包括电路晶体管，电容器部分，第一连接部分和第二连接部分。响应于通过栅电极施加的控制信号，电路晶体管通过源电极输出栅极信号。电容器部分包括第一电极，形成在第一电极上的第二电极和形成在第二电极上的第三电极。第一连接部电连接电路晶体管的栅电极和电容器部的第二电极。第二连接部分电连接电路晶体管的源电极和电容器部分的第一电极。因此，可以减小栅极驱动电路的集成尺寸，并且可以提高栅极驱动电路的可靠性。

56. 发明申请

US20110122117A1 DISPLAY PANEL 有权
标题翻译：显示面板
公开(公告)号：US20110122117A1
公开(公告)日：2011-05-26
申请号：US12949931
申请日：2010-11-19
申请人： Jae-Hoon Lee , Seung-Hwan Moon , Yong-Soon Lee , Young-Su Kim , Chang-Ho Lee , Whee-Won Lee , Jun-Yong Song , Yu-Han Bae
发明人： Jae-Hoon Lee , Seung-Hwan Moon , Yong-Soon Lee , Young-Su Kim , Chang-Ho Lee , Whee-Won Lee , Jun-Yong Song , Yu-Han Bae
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G09G2330/021 , G11C19/28
摘要： A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.
摘要翻译：显示面板包括非晶硅栅极驱动器，其中比栅极驱动器输出的栅极截止电压更低的电压作为低电压传输信号施加到相邻级。

57. 发明申请

US20100207928A1 Gate Driving Circuit and Display Device Having the Gate Driving Circuit 有权
标题翻译：具有栅极驱动电路的栅极驱动电路和显示装置
公开(公告)号：US20100207928A1
公开(公告)日：2010-08-19
申请号：US12616604
申请日：2009-11-11
申请人： Jae-Hoon Lee , Jun-Yong Song , Hoi-Sik Moon , Yong-Soon Lee
发明人： Jae-Hoon Lee , Jun-Yong Song , Hoi-Sik Moon , Yong-Soon Lee
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： A gate driving circuit includes a plurality of stages connected to each other. An m-th stage (‘m’ is a natural number) of the stages includes a pull-up part, a pull-down part, a first holding part and a second holding part. The pull-up part outputs a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage applied to a first output control part. The pull-down part pulls down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal. The first holding part holds a voltage applied to the first output control part as a second low voltage having a level lower than the first low voltage. The second holding part holds a low voltage of the m-th gate signal to the first low voltage.
摘要翻译：栅极驱动电路包括彼此连接的多个级。第m级（“m”是自然数）级包括上拉部分，下拉部分，第一保持部分和第二保持部分。响应于施加到第一输出控制部分的高电压，上拉部分输出作为第m门信号的高电压的时钟信号的高电压。下拉部分响应于第（m + 1）门信号的高电压将第m门信号的高电压下拉到第一低电压。第一保持部分将施加到第一输出控制部分的电压保持为具有低于第一低电压电平的第二低电压。第二保持部将第m栅极信号的低电压保持为第一低电压。

58. 发明授权

US07586358B2 Level shifter and driving method 有权
标题翻译：电平转换器和驱动方式
公开(公告)号：US07586358B2
公开(公告)日：2009-09-08
申请号：US11771138
申请日：2007-06-29
申请人： Kee-Chan Park , Min-Koo Han , Woo-Jin Nam , Jae-Hoon Lee
发明人： Kee-Chan Park , Min-Koo Han , Woo-Jin Nam , Jae-Hoon Lee
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , G09G3/3611 , G09G3/3648 , G09G2300/0408 , G09G2310/0289 , G09G2310/08
摘要： A level shifter includes; a level conversion unit which receives a first input signal and a second input signal, wherein the second input signal is an inversion of the first input signal, and generates a first output signal having substantially a same phase of the first input signal and a voltage which is higher than the first input signal and a second output signal having substantially a same phase as the first input signal and a voltage which is lower than the first input signal; and wherein the level shifter further includes an amplifying unit which receives the first and second output signals and generates a third output signal having substantially a same phase as the first input signal and an amplitude which is greater than the first input signal.
摘要翻译：电平转换器包括：电平转换单元，其接收第一输入信号和第二输入信号，其中所述第二输入信号是所述第一输入信号的反相，并且产生具有与所述第一输入信号基本上相同相位的第一输出信号和高于第一输入信号，第二输出信号具有与第一输入信号基本相同的相位和低于第一输入信号的电压; 并且其中所述电平移位器还包括放大单元，其接收所述第一和第二输出信号，并产生具有与所述第一输入信号基本相同的相位的第三输出信号和大于所述第一输入信号的幅度。

59. 发明申请

US20090216512A9 Method and apparatus for indirectly simulating a semiconductor integrated circuit 失效
标题翻译：用于间接模拟半导体集成电路的方法和装置
公开(公告)号：US20090216512A9
公开(公告)日：2009-08-27
申请号：US11888535
申请日：2007-08-01
申请人： Jae-Hoon Lee
发明人： Jae-Hoon Lee
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5009 , G06F2217/62 , G06F2217/66 , G06F2217/84
摘要： A method and an apparatus for indirectly simulating a semiconductor integrated circuit (IC) are described. A circle chain is formed using input pins and output pins to provide an intellectual property (IP) core model that substitutes for a real IP core circuit. A test bench for the IP core model is generated, the semiconductor IC that includes the IP core model is integrated using the generated test bench, and the semiconductor IC is simulated.
摘要翻译：描述用于间接模拟半导体集成电路（IC）的方法和装置。使用输入引脚和输出引脚形成环形链，以提供替代真实IP核心电路的知识产权（IP）核心模型。生成IP核心模型的测试台，使用生成的测试台集成了包含IP核模型的半导体IC，模拟半导体IC。

60. 发明申请

US20060256057A1 Pixel structure using voltage programming-type for active matrix organic light emitting device 有权
标题翻译：使用有源矩阵有机发光器件的电压编程类型的像素结构
公开(公告)号：US20060256057A1
公开(公告)日：2006-11-16
申请号：US11412525
申请日：2006-04-27
申请人： Min-Koo Han , Jae-Hoon Lee
发明人： Min-Koo Han , Jae-Hoon Lee
IPC分类号： G09G3/36
CPC分类号： G09G3/3258 , G09G2300/0819 , G09G2300/0842 , G09G2320/0233
摘要： A pixel structure using a voltage programming type active matrix organic light emitting diode (OLED) which can minimize a current deterioration phenomenon is disclosed. The pixel structure includes a fifth TFT receiving an external management signal EMS through its gate, having a drain region connected to a cathode part of an OLED, and receiving an input of an OLED current through its source-drain current path when the OLED emits light, a fourth TFT receiving a set scan signal SCAN through its gate and having source and drain regions connected to gate and drain parts of a third TFT T3, respectively, the third TFT T3 being a current driving transistor for determining the OLED current when the OLED emits light, a capacitor C having upper and lower plates connected to the gate part of the third TFT T3 and a ground voltage VSS, respectively, a first TFT receiving the SCAN signal through its gate and transferring a data voltage to a source region of the third TFT T3, a second TFT receiving the EMS signal through its gate and connecting the lower part of the capacitor C to the source region of the third TFT T3, and a sixth TFT having source and drain regions connected to an external clock signal CLK and the gate region of the third TFT T3, respectively, and having a gate connected to the gate part of the third TFT T3. An anode part of the OLED receives a voltage VDD.
摘要翻译：公开了一种可以使电流劣化现象最小化的电压编程型有源矩阵有机发光二极管（OLED）的像素结构。像素结构包括通过其栅极接收外部管理信号EMS的第五TFT，具有连接到OLED的阴极部分的漏极区域，并且当OLED发光时，通过其源极 - 漏极电流路径接收OLED电流的输入，第四TFT通过其栅极接收设置的扫描信号SCAN，并且分别具有连接到第三TFT T 3的栅极和漏极部分的源极和漏极区域，第三TFT T 3是用于确定OLED电流的电流驱动晶体管， OLED发光，具有连接到第三TFT T 3的栅极部分的上板和下板的电容器C和接地电压VSS分别通过其栅极接收SCAN信号的第一TFT并将数据电压传送到源极区域，第二TFT通过其栅极接收EMS信号并将电容器C的下部连接到第三TFT T 3的源极区域，以及第六TFT，其具有源极和栅极连接到外部时钟信号CLK的n个区域和第三TFT T 3的栅极区域，并且具有连接到第三TFT T 3的栅极部分的栅极。 OLED的阳极部分接收电压VDD。

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