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1. 发明申请

US20100045656A1 Display driver with charge pumping signals synchronized to different clocks for multiple modes 有权
标题翻译：显示驱动器，电荷泵浦信号与多种模式的不同时钟同步
公开(公告)号：US20100045656A1
公开(公告)日：2010-02-25
申请号：US12590052
申请日：2009-11-02
申请人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
发明人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
IPC分类号： G09G5/00
CPC分类号： G09G5/006 , G09G3/3611 , G09G5/18
摘要： A display driver generates a respective charge pumping signal and respective driving signals synchronized to a respective same clock signal for each of the CPU and video interface modes. Because such respective signals are synchronized to a respective same clock signal, the noise superimposed on the driving signals applied on a display panel is regular and uniform across the whole display panel, for each of the CPU and video interface modes. Accordingly, affects of such regular noise are advantageously not noticeable to the human eye, for both the video and CPU interface modes of operation.
摘要翻译：显示驱动器针对CPU和视频接口模式中的每一个产生相应的电荷泵浦信号和与相应的相同时钟信号同步的各个驱动信号。因为这些各个信号被同步到相应的相同的时钟信号，所以叠加在施加在显示面板上的驱动信号上的噪声对于CPU和视频接口模式的每一个在整个显示面板上是规则和均匀的。因此，对于视频和CPU接口操作模式，这种正常噪声的影响对人眼而言是不利的。

2. 发明授权

US07633498B2 Display driver with charge pumping signals synchronized to different clocks for multiple modes 有权
标题翻译：显示驱动器，电荷泵浦信号与多种模式的不同时钟同步
公开(公告)号：US07633498B2
公开(公告)日：2009-12-15
申请号：US10987783
申请日：2004-11-12
申请人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
发明人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G5/006 , G09G3/3611 , G09G5/18
摘要： A display driver generates a respective charge pumping signal and respective driving signals synchronized to a respective same clock signal for each of the CPU and video interface modes. Because such respective signals are synchronized to a respective same clock signal, the noise superimposed on the driving signals applied on a display panel is regular and uniform across the whole display panel, for each of the CPU and video interface modes. Accordingly, affects of such regular noise are advantageously not noticeable to the human eye, for both the video and CPU interface modes of operation.
摘要翻译：显示驱动器针对CPU和视频接口模式中的每一个产生相应的电荷泵浦信号和与相应的相同时钟信号同步的各个驱动信号。因为这些各个信号被同步到相应的相同的时钟信号，所以叠加在施加在显示面板上的驱动信号上的噪声对于CPU和视频接口模式的每一个在整个显示面板上是规则和均匀的。因此，对于视频和CPU接口操作模式，这种正常噪声的影响对人眼而言是不利的。

3. 发明申请

US20050110784A1 Display driver with charge pumping signals synchronized to different clocks for multiple modes 有权
标题翻译：显示驱动器，电荷泵浦信号与多种模式的不同时钟同步
公开(公告)号：US20050110784A1
公开(公告)日：2005-05-26
申请号：US10987783
申请日：2004-11-12
申请人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
发明人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00 , G09G5/18
CPC分类号： G09G5/006 , G09G3/3611 , G09G5/18
摘要： A display driver generates a respective charge pumping signal and respective driving signals synchronized to a respective same clock signal for each of the CPU and video interface modes. Because such respective signals are synchronized to a respective same clock signal, the noise superimposed on the driving signals applied on a display panel is regular and uniform across the whole display panel, for each of the CPU and video interface modes. Accordingly, affects of such regular noise are advantageously not noticeable to the human eye, for both the video and CPU interface modes of operation.
摘要翻译：显示驱动器针对CPU和视频接口模式中的每一个产生相应的电荷泵浦信号和与相应的相同时钟信号同步的各个驱动信号。因为这些各个信号被同步到相应的相同的时钟信号，所以叠加在施加在显示面板上的驱动信号上的噪声对于CPU和视频接口模式的每一个在整个显示面板上是规则和均匀的。因此，对于视频和CPU接口操作模式，这种正常噪声的影响对人眼而言是不利的。

4. 发明授权

US08416233B2 Display driver with charge pumping signals synchronized to different clocks for multiple modes 有权
公开(公告)号：US08416233B2
公开(公告)日：2013-04-09
申请号：US12590052
申请日：2009-11-02
申请人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
发明人： Won-Sik Kang , Jae-Koo Lee , Jae-Hoon Lee
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G5/006 , G09G3/3611 , G09G5/18
摘要： A display driver generates a respective charge pumping signal and respective driving signals synchronized to a respective same clock signal for each of the CPU and video interface modes. Because such respective signals are synchronized to a respective same clock signal, the noise superimposed on the driving signals applied on a display panel is regular and uniform across the whole display panel, for each of the CPU and video interface modes. Accordingly, affects of such regular noise are advantageously not noticeable to the human eye, for both the video and CPU interface modes of operation.

5. 发明申请

US20140253532A1 DISPLAY DRIVING DEVICE, DISPLAY APPARATUS AND METHOD FOR OPERATING THE SAME 有权
标题翻译：显示驱动装置，显示装置及其操作方法
公开(公告)号：US20140253532A1
公开(公告)日：2014-09-11
申请号：US14178376
申请日：2014-02-12
申请人： Jae-Hyuck Woo , Won-Sik Kang , Yang-Hyo Kim , In-Suk Kim , Jong-Kon Bae
发明人： Jae-Hyuck Woo , Won-Sik Kang , Yang-Hyo Kim , In-Suk Kim , Jong-Kon Bae
IPC分类号： G09G5/00
CPC分类号： G09G5/00 , G09G3/20 , G09G3/3685 , G09G2300/0408 , G09G2300/0426 , G09G2310/0275 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291
摘要： A display driving device includes a first source amplifier that receives first display data and supplies a first pixel voltage to a first pixel based on the received first display data, and a second source amplifier that receives second display data and first control data and supplies a second pixel voltage to a second pixel based on the received second display data and first control data. The second source amplifier has a first stage in which a first process is performed on an input signal based on the second display data, and a second stage in which a second process is performed on the first processed input signal to output the second pixel voltage. The first source amplifier may be configured to conditionally supply the first pixel voltage to the second pixel.
摘要翻译：显示驱动装置包括：第一源放大器，其接收第一显示数据并且基于接收到的第一显示数据将第一像素电压提供给第一像素;以及第二源放大器，其接收第二显示数据和第一控制数据，并且提供第二基于所接收的第二显示数据和第一控制数据，将像素电压提供给第二像素。第二源放大器具有第一级，其中基于第二显示数据对输入信号执行第一处理，以及第二级，其中对第一处理的输入信号执行第二处理以输出第二像素电压。第一源极放大器可以被配置为有条件地将第一像素电压提供给第二像素。

6. 发明授权

US08042020B2 Data error correction circuit, integrated circuit for data error correction, and method of performing data error correction 有权
标题翻译：数据纠错电路，数据纠错用集成电路及数据纠错方法
公开(公告)号：US08042020B2
公开(公告)日：2011-10-18
申请号：US11772985
申请日：2007-07-03
申请人： Won-Sik Kang , Seong-Cheol Kim
发明人： Won-Sik Kang , Seong-Cheol Kim
IPC分类号： G11C29/00
CPC分类号： H03M13/43
摘要： A data error correction circuit includes a plurality of one-bit registers, a data error detection unit and a data error correction unit. The data error detection unit detects whether all the data values stored in the plurality of the registers are equal. The data correction unit determines a correct data value based upon each of the stored data values, and corrects each of the data values into the determined correct data value if the data values are not equal. Therefore, the data error correction circuit may correct a data error due to electrostatic discharge (ESD) or electromagnetic interference (EMI).
摘要翻译：数据纠错电路包括多个一位寄存器，数据错误检测单元和数据错误校正单元。数据错误检测单元检测存储在多个寄存器中的所有数据值是否相等。数据校正单元基于每个存储的数据值确定正确的数据值，并且如果数据值不相等，则将每个数据值校正为确定的正确数据值。因此，数据纠错电路可以校正由于静电放电（ESD）或电磁干扰（EMI）引起的数据误差。

7. 发明授权

US07627799B2 Panel driving circuit that generates panel test pattern and panel test method thereof 有权
标题翻译：生成面板测试图案的面板驱动电路及其面板测试方法
公开(公告)号：US07627799B2
公开(公告)日：2009-12-01
申请号：US11046178
申请日：2005-01-28
申请人： Won-Sik Kang , Jae-Goo Lee
发明人： Won-Sik Kang , Jae-Goo Lee
IPC分类号： G01R31/28
CPC分类号： G01R31/318378 , G09G3/006 , G09G3/3611 , G09G3/3648 , G09G5/006 , G09G2330/02 , G09G2340/125 , H04N5/06 , H04N17/04
摘要： A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.
摘要翻译：提供了产生面板测试图案的面板驱动电路和测试面板的方法。驱动电路包括图案生成单元和选择单元。图案生成单元响应系统时钟并产生模式测试数据和模式测试信号。选择单元响应于测试信号，并且选择并输出（a）从模式生成单元输出的模式测试数据和模式测试信号，或者（b）直接应用的模式测试数据和模式测试信号从外部。驱动电路和面板测试方法使用系统时钟产生驱动电路内的面板测试数据，水平同步信号，垂直同步信号和数据激活信号，从而可以执行面板的测试而不使用单独的测试设备。

8. 发明申请

US20080211466A1 Voltage Generators Implementing Boosting Schemes for Generating Boosting Voltages and Related Liquid Crystal Displays (LCDS) and Methods 失效
标题翻译：电压发生器实现用于生成升压电压和相关液晶显示器（LCDS）和方法的升压方案
公开(公告)号：US20080211466A1
公开(公告)日：2008-09-04
申请号：US11963213
申请日：2007-12-21
申请人： Jae Ho Park , Won-Sik Kang
发明人： Jae Ho Park , Won-Sik Kang
IPC分类号： G05F1/10
CPC分类号： G09G3/3696 , H02M3/07
摘要： A voltage generators is provided including a boosting circuit and a boosting control circuit. The boosting circuit is configured to boost a power voltage to generate first through fourth voltages. The boosting control circuit is configured to control the boosting circuit to enable the first through fourth voltages to be generated in sequence, such that when a current voltage of the first through fourth voltages is boosted to a predetermined level, a voltage next to the current voltage is generated. Related liquid crystal displays and methods are also provided.
摘要翻译：提供了包括升压电路和升压控制电路的电压发生器。升压电路被配置为升高电源电压以产生第一至第四电压。升压控制电路被配置为控制升压电路以使得能够依次产生第一至第四电压，使得当第一至第四电压的电流电压升压到预定电平时，与当前电压相邻的电压被生成。还提供了相关的液晶显示器和方法。

9. 发明授权

US07161864B2 Bit refresh circuit for refreshing register bit values, integrated circuit device having the same, and method of refreshing register bit values 有权
标题翻译：用于刷新寄存器位值的位刷新电路，具有相同的集成电路器件以及刷新寄存器位值的方法
公开(公告)号：US07161864B2
公开(公告)日：2007-01-09
申请号：US11123263
申请日：2005-05-07
申请人： Won-Sik Kang , Jae-Goo Lee , Jae-Hyuck Woo
发明人： Won-Sik Kang , Jae-Goo Lee , Jae-Hyuck Woo
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C7/02 , G11C7/1006 , G11C2029/0409 , G11C2207/104
摘要： There is provided a bit refresh circuit and method of checking errors in bit values of a register and refreshing the bit values, and an integrated circuit comprising the bit refresh circuit. The integrated circuit includes a refresh unit checking whether or not the bit values of the register storing data used to control the operations of a logic circuit changes due to external noise. The refresh unit checks bit-by-bit whether or not there are errors in the bit values due to the external noise. If there are errors in the bit values of the register, the data of the associated bit values stored in a memory are refreshed into the register.
摘要翻译：提供了位刷新电路和检查寄存器的位值中的错误并刷新位值的方法，以及包括位刷新电路的集成电路。集成电路包括刷新单元，检查用于控制逻辑电路的操作的寄存器存储数据的位值是否由于外部噪声而改变。刷新单元逐位检查由于外部噪声引起的位值是否有错误。如果寄存器的位值存在错误，存储在存储器中的相关位值的数据将刷新到寄存器中。

10. 发明申请

US20050093808A1 Timing controller and method for reducing liquid crystal display operating current 有权
标题翻译：定时控制器和减少液晶显示工作电流的方法
公开(公告)号：US20050093808A1
公开(公告)日：2005-05-05
申请号：US10981056
申请日：2004-11-04
申请人： Won-Sik Kang , Jae-Goo Lee
发明人： Won-Sik Kang , Jae-Goo Lee
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00
CPC分类号： G09G3/3685 , G09G3/3674 , G09G2330/021
摘要： Provided are a timing controller, a liquid crystal display (LCD) driver including the same, and a method of outputting display data, where the timing controller receives a vertical synchronous signal and a data enable signal, generates an internal data enable signal having a period that is longer than the period of the data enable signal in response to the vertical synchronous signal and the data enable signal, and updates a memory using the internal data enable signal; where the LCD driver including the timing controller outputs display data stored in a memory device based on the internal data enable signal; where a data line driving circuit drives data lines based on the output display data; and where the method of outputting display data is performed by the LCD driver.
摘要翻译：提供了一种定时控制器，包括该定时控制器的液晶显示器（LCD）驱动器和输出显示数据的方法，其中定时控制器接收垂直同步信号和数据使能信号，产生具有周期的内部数据使能信号其响应于垂直同步信号和数据使能信号长于数据使能信号的周期，并且使用内部数据使能信号来更新存储器; 其中包括定时控制器的LCD驱动器基于内部数据使能信号输出存储在存储器件中的显示数据; 数据线驱动电路基于输出显示数据驱动数据线; 并且其中由LCD驱动器执行输出显示数据的方法。

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