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    • 54. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US4831592A
    • 1989-05-16
    • US68521
    • 1987-07-01
    • Hiroto NakaiHiroshi IwahashiMasamichi AsanoIsao SatoShigeru KumagaiKazuto Suzuki
    • Hiroto NakaiHiroshi IwahashiMasamichi AsanoIsao SatoShigeru KumagaiKazuto Suzuki
    • G11C16/30G11C16/32
    • G11C16/32G11C16/30
    • A nonvolatile semiconductor memory device includes a pulse signal generator for applying a pulse signal to a capacitor, a first diode connected at an anode to the capacitor, a charging circuit for charging the capacitor in a programming mode, a voltage limiter for preventing a potential at the output node from increasing above a predetermined level, memory cells of nonvolatile MOS transistors, a load MOS transistor connected to a high-voltage terminal, a row decoder for selecting a set of memory cells arranged in one row, column gate MOS transistors connected between respective sets of memory cells arranged in one column and the load MOS transistor, a data generator responsive to the voltage at the output node to turn on or off the load MOS transistor, and a column decoder responsive to the voltage at the output node to selectively energize the column gate MOS transistors. It further comprises a second diode connected between the cathode of the first diode and the output node, and a discharging circuit for discharging the cathode of the first diode to a reference voltage level during a time other than a programming mode.
    • 一种非易失性半导体存储器件,包括用于向电容器施加脉冲信号的脉冲信号发生器,连接到电容器的阳极的第一二极管,以编程模式对电容器充电的充电电路,用于防止电位 输出节点从预定电平上升,非易失性MOS晶体管的存储单元,连接到高电压端子的负载MOS晶体管,用于选择排列成一行的一组存储单元的行解码器,连接在 设置在一列中的各组存储单元和负载MOS晶体管,响应于输出节点处的电压以打开或关闭负载MOS晶体管的数据发生器,以及响应于输出节点处的电压以选择性地 激励列栅极MOS晶体管。 其还包括连接在第一二极管的阴极和输出节点之间的第二二极管和用于在编程模式之外的时间期间将第一二极管的阴极放电到参考电压电平的放电电路。