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51. 发明申请

US20050182914A1 Synchronous dram system with control data 审中-公开
标题翻译：具有控制数据的同步播放系统
公开(公告)号：US20050182914A1
公开(公告)日：2005-08-18
申请号：US11103698
申请日：2005-04-11
申请人： Masashi Hashimoto , Gene Frantz , John Moravec , Jean-Pierre Dolait
发明人： Masashi Hashimoto , Gene Frantz , John Moravec , Jean-Pierre Dolait
IPC分类号： G11C7/10 , G11C8/02 , H04B7/185 , G06F12/06
CPC分类号： G09G5/391 , G11C7/103 , G11C7/1036 , G11C7/1072 , G11C7/1075 , H04B7/18502
摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
摘要翻译：公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。存储器电路（14）被串行和随机地访问。地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

52. 发明授权

US06800827B2 Method for efficient laser isotope separation and enrichment of silicon 失效
标题翻译：高效激光同位素分离和富集硅的方法
公开(公告)号：US06800827B2
公开(公告)日：2004-10-05
申请号：US10212865
申请日：2002-08-07
申请人： Atsushi Yokoyama , Hironori Ohba , Masashi Hashimoto , Takemasa Shibata , Shigeyoshi Arai , Takeshi Ishii , Akio Ohya
发明人： Atsushi Yokoyama , Hironori Ohba , Masashi Hashimoto , Takemasa Shibata , Shigeyoshi Arai , Takeshi Ishii , Akio Ohya
IPC分类号： B01D500
CPC分类号： B01D59/34
摘要： A method for laser-assisted separation and enrichment of silicon isotopes such as 28Si, 29Si and 30Si on the basis of infrared multiple-photon dissociation of silicon halides represented by Si2F6, wherein the silicon halides are irradiated synchronously with multiple infrared pulsed laser beams at different wavelengths.
摘要翻译：基于由Si 2 F 6表示的卤化硅的红外多光子解离的硅同位素如28 Si，30 Si和30 Si的激光辅助分离和富集的方法，其中卤化硅被照射与不同波长的多个红外脉冲激光束同步。

53. 发明授权

US06732224B2 System with control data buffer for transferring streams of data 失效
标题翻译：具有用于传送数据流的控制数据缓冲器的系统
公开(公告)号：US06732224B2
公开(公告)日：2004-05-04
申请号：US10449583
申请日：2003-05-30
申请人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
发明人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
IPC分类号： G11C804
CPC分类号： G09G5/391 , G11C7/103 , G11C7/1036 , G11C7/1072 , G11C7/1075 , H04B7/18502
摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
摘要翻译：公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。存储器电路（14）被串行和随机地访问。地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

54. 发明授权

US06392947B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06392947B1
公开(公告)日：2002-05-21
申请号：US09186315
申请日：1998-11-04
申请人： Masashi Hashimoto
发明人： Masashi Hashimoto
IPC分类号： G11C700
CPC分类号： G11C7/1051
摘要： To efficiently access pixel data stored in memory in the X direction and Y direction when carrying out error correction processing. In a data output section 10, a pixel block consisting the desired 2×2 pixel data W1-W4 is selected by inputting a address, and pixel data continuously aligned in an arbitrary direction, that is, in the X direction or Y direction, are output inputting output pixel selection signals V1 and V2. Specifically, two pixels W1, W2, or W3, W4, which are continuously aligned in the X direction, are selected when signals V1 and V2=0 and V1=0 and V2=1, and two arbitrary pixels W1, W3 or W2, W4, which are continuously aligned in the Y direction, are selected when signal V1=1 and V2=0 and V1 and V2=1.
摘要翻译：在进行纠错处理时，有效地存取存储在X方向和Y方向的存储器中的像素数据。在数据输出部10中，通过输入地址来选择构成期望的2×2像素数据W1-W4的像素块，并且在任意方向，即在X方向或Y方向上连续排列的像素数据被输出输出像素选择信号V1和V2。具体地说，当信号V1和V2 = 0，V1 = 0和V2 = 1时，选择在X方向上连续排列的两个像素W1，W2或W3，W4，并且两个任意像素W1，W3或W2，当信号V1 = 1和V2 = 0，V1和V2 = 1时，选择在Y方向上连续排列的W4。

55. 发明授权

US5917839A Apparatus and method for a read-modify-write operation in a dynamic random access memory 失效
标题翻译：在动态随机存取存储器中进行读 - 修改 - 写操作的装置和方法
公开(公告)号：US5917839A
公开(公告)日：1999-06-29
申请号：US863851
申请日：1997-05-27
申请人： Masashi Hashimoto , Anjana Ghosh
发明人： Masashi Hashimoto , Anjana Ghosh
IPC分类号： G06F11/10 , H03M13/09 , H03M13/00
CPC分类号： G06F11/1056 , H03M13/098
摘要： In a dynamic random access memory unit 10, a circuit, 61.sub.0 -61.sub.N.sbsb.--.sub.1, 615, and 617, is provided in which a non-change of each address signal of an address signal group during a next consecutive clock cycle blocks the application of the read activation control signal to the memory unit 10. In this manner, the memory unit 10 is inactive (i.e., does not perform a read operation) during the modify portion of a read-modify-write operation so that potential conflicts in the operation of the memory unit 10 are avoided.
摘要翻译：在动态随机存取存储器单元10中，提供电路610-61N-1,615和617，其中在下一个连续时钟周期期间地址信号组的每个地址信号的不变化阻止了读取激活控制信号发送到存储器单元10.以这种方式，在读取 - 修改 - 写入操作的修改部分期间，存储器单元10不活动（即，不执行读取操作），使得操作中的潜在冲突避免了存储器单元10。

56. 发明授权

US5910926A Apparatus and method for a dynamic random access architecture 失效
标题翻译：一种用于动态随机存取架构的装置和方法
公开(公告)号：US5910926A
公开(公告)日：1999-06-08
申请号：US923695
申请日：1997-09-04
申请人： Masashi Hashimoto
发明人： Masashi Hashimoto
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/407 , G11C8/00
CPC分类号： G11C7/06
摘要： A memory unit 30 is provided with a first and second sense amplifier array 32A and 32B. The storage cells 31 of the memory unit are coupled to both sense amplifier arrays. A control unit 34 is provided which controls the operation of the two sense amplifier arrays. The control unit determines through which sense amplifier array data signals are transferred to and from the storage cells. The sense amplifier array not exchanging signals with the I/O terminals can perform the precharge operations and write-back operations. Synchronous operation of the memory unit and a data processing unit can be maintained by alternating the sense amplifier array performing the current memory access operation.
摘要翻译：存储单元30设置有第一和第二读出放大器阵列32A和32B。存储单元的存储单元31耦合到两个读出放大器阵列。提供控制单元34，其控制两个读出放大器阵列的操作。控制单元确定哪个读出放大器阵列的数据信号被传送到和从存储单元传送。不与I / O端子交换信号的读出放大器阵列可以执行预充电操作和回写操作。可以通过交替执行当前存储器存取操作的读出放大器阵列来保持存储器单元和数据处理单元的同步操作。

57. 发明授权

US5748544A Apparatus and method for reducing test time of the data retention parameter in a dynamic random access memory 失效
标题翻译：用于减少动态随机存取存储器中的数据保留参数的测试时间的装置和方法
公开(公告)号：US5748544A
公开(公告)日：1998-05-05
申请号：US801984
申请日：1997-02-19
申请人： Masashi Hashimoto
发明人： Masashi Hashimoto
IPC分类号： G11C11/401 , G11C11/4074 , G11C11/409 , G11C29/00 , G11C29/50
CPC分类号： G11C29/028 , G11C11/4074 , G11C29/50 , G11C29/50016 , G11C11/401 , G11C2029/5004
摘要： In a dynamic random access memory device, the time required for implementation of memory cell data retention time testing procedures can be reduced by changing the voltage level(s) applied to the components of the storage cell when compared to the voltages applied during the typical memory cell operation. By changing the voltage(s) applied to the components, the difference in the bitlines detected by the sense amplifier will be reduced. Because to the reduced bitline voltage difference, the decay of the charge on the storage cell causes a reduction in the data retention time. The data retention time is reduced in manner related to the typical memory cell operation. The altered voltage(s) can be applied to the storage cell bitlines and/or to the storage cell dummy capacitances.
摘要翻译：在动态随机存取存储器件中，通过改变与在典型存储器期间施加的电压相比施加到存储单元的组件的电压电平，可以减少实现存储单元数据保持时间测试程序所需的时间电池操作。通过改变施加到分量的电压，由读出放大器检测的位线的差将减小。因为对于降低的位线电压差，存储单元上的电荷的衰减导致数据保持时间的减少。与典型的存储单元操作相关的方式减少数据保留时间。改变的电压可以被施加到存储单元位线和/或存储单元虚拟电容。

58. 发明授权

US5689467A Apparatus and method for reducing test time of the data retention parameter in a dynamic random access memory 失效
标题翻译：用于减少动态随机存取存储器中的数据保留参数的测试时间的装置和方法
公开(公告)号：US5689467A
公开(公告)日：1997-11-18
申请号：US565495
申请日：1995-11-30
申请人： Masashi Hashimoto
发明人： Masashi Hashimoto
IPC分类号： G11C11/401 , G11C11/4074 , G11C11/409 , G11C29/00 , G11C29/50
CPC分类号： G11C29/028 , G11C11/4074 , G11C29/50 , G11C29/50016 , G11C11/401 , G11C2029/5004
摘要： In a dynamic random access memory device, the time required for implementation of memory cell data retention time testing procedures can be reduced by changing the voltage level(s) applied to the components of the storage cell when compared to the voltages applied during the typical memory cell operation. By changing the voltage(s) applied to the components, the difference in the bitlines detected by the sense amplifier will be reduced. Because to the reduced bitline voltage difference, the decay of the charge on the storage cell causes a reduction in the data retention time. The data retention time is reduced in manner related to the typical memory cell operation. The altered voltage(s) can be applied to the storage cell bitlines and/or to the storage cell dummy capacitances.
摘要翻译：在动态随机存取存储器件中，通过改变与在典型存储器期间施加的电压相比施加到存储单元的组件的电压电平，可以减少实现存储单元数据保持时间测试程序所需的时间电池操作。通过改变施加到分量的电压，由读出放大器检测的位线的差将减小。因为对于降低的位线电压差，存储单元上的电荷的衰减导致数据保持时间的减少。与典型的存储单元操作相关的方式减少数据保留时间。改变的电压可以被施加到存储单元位线和/或存储单元虚拟电容。

59. 发明授权

US5680367A Process for controlling writing data to a DRAM array 失效
标题翻译：用于控制将数据写入DRAM阵列的处理
公开(公告)号：US5680367A
公开(公告)日：1997-10-21
申请号：US480637
申请日：1995-06-07
申请人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
发明人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
IPC分类号： G11C7/10 , G11C8/02 , H04B7/185 , G11C8/00
CPC分类号： G09G5/391 , G11C7/103 , G11C7/1036 , G11C7/1072 , G11C7/1075 , H04B7/18502
摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
摘要翻译：公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。存储器电路（14）被串行和随机地访问。地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

60. 发明授权

US5574298A Substrate contact for gate array base cell and method of forming same 失效
标题翻译：栅极阵列基体的基板接触及其形成方法
公开(公告)号：US5574298A
公开(公告)日：1996-11-12
申请号：US521080
申请日：1995-08-29
申请人： Masashi Hashimoto , Louis N. Hutter , S. Shivaling Mahant-Shetti
发明人： Masashi Hashimoto , Louis N. Hutter , S. Shivaling Mahant-Shetti
IPC分类号： H01L21/82 , H01L27/118 , H01L27/10
CPC分类号： H01L27/11803 , Y10S257/901
摘要： A method for forming a gate array substrate contact and the contact resulting therefrom includes the steps of etching off polysilicon gate layers at the same time as cutting the polysilicon to form the gate array base cell (10). The method includes forming openings (40, 42, and 44) in the second insulating layer (34) and insulating layer (30) to connect a lead (46, 48, and 50) to the underlying substrate.
摘要翻译：一种用于形成栅极阵列基板接触的方法和由其产生的接触包括以下步骤：在切割多晶硅的同时蚀刻多晶硅栅极层以形成栅阵列基电池（10）。该方法包括在第二绝缘层（34）和绝缘层（30）中形成开口（40,42和44），以将引线（46,48和50）连接到下面的基板。

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