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51. 发明授权

US5950937A Alumina-zirconia sintered body, production thereof, and impact grinder using said alumina-zirconia sintered body 有权
公开(公告)号：US5950937A
公开(公告)日：1999-09-14
申请号：US197535
申请日：1998-11-23
申请人： Akihito Iwai , Hiroshi Wada , Katsumi Matsumoto , Sosuke Naito , Yoshihiko Imai , Hideki Nakamura , Hiroaki Tanaka
发明人： Akihito Iwai , Hiroshi Wada , Katsumi Matsumoto , Sosuke Naito , Yoshihiko Imai , Hideki Nakamura , Hiroaki Tanaka
IPC分类号： C04B35/10 , B02C13/28 , C04B35/119 , C04B35/48 , C04B35/488
CPC分类号： C04B35/4885 , B02C13/28 , C04B35/119
摘要： An alumina-zirconia sintered body comprising 92 to 35% by weight of aluminum oxide and 8 to 65% by weight of zirconium oxide having mainly tetragonal system, and 0.2 to 5 parts by weight of silicon oxide per 100 parts by weight of the total of aluminum oxide and zirconium oxide, and having a relative density of 95% or more, has improved wear resistance and suitable for use in an impact grinder.

52. 发明授权

US5938762A Method and apparatus for performing exception processing routine in pipeline processing 失效
标题翻译：在流水线处理中执行异常处理程序的方法和装置
公开(公告)号：US5938762A
公开(公告)日：1999-08-17
申请号：US726753
申请日：1996-10-07
申请人： Hiroshi Hayakawa , Harutsugu Fukumoto , Hiroaki Tanaka
发明人： Hiroshi Hayakawa , Harutsugu Fukumoto , Hiroaki Tanaka
IPC分类号： G06F9/32 , G06F9/38 , G06F9/46
CPC分类号： G06F9/322 , G06F9/3861
摘要： An information processing apparatus and method, such that when an interruption occurs in a microprocessor, an exception processing sequence control is started, a program condition of an interrupted program and an address of the interrupted program are saved in a RAM, a program address of a jump instruction is read out from an exception processing generating source and is set in a program counter, and the exception processing sequence control is stopped. Thereafter, a normal processing sequence control is started, the jump instruction is read out from a ROM, an address of an exception processing vector is calculated according to the jump instruction, the exception processing vector is read out from the ROM, a branch address of an exception processing routine indicated by the exception processing vector is set in the program counter, and an operation state of the microprocessor is branched to the exception processing routine. Thereafter, the normal processing sequence control is stopped, and the exception processing routine is performed in the exception processing sequence control.
摘要翻译：一种信息处理装置和方法，当在微处理器中发生中断时，开始异常处理顺序控制，中断程序的程序条件和中断程序的地址被保存在RAM中，程序地址从异常处理生成源读出跳转指令，并将其设置在程序计数器中，并停止异常处理顺序控制。此后，开始通常的处理顺序控制，从ROM读出跳转指令，根据跳转指令计算出异常处理向量的地址，从ROM中读出异常处理向量，分支地址在程序计数器中设置由异常处理向量指示的异常处理程序，并且将微处理器的操作状态分支到异常处理程序。此后，停止正常处理顺序控制，并且在异常处理顺序控制中执行异常处理程序。

53. 发明授权

US5936486A Active filter with surface acoustic wave resonator filter having multiple resonant modes 失效
标题翻译：具有多个谐振模式的声表面波谐振滤波器的有源滤波器
公开(公告)号：US5936486A
公开(公告)日：1999-08-10
申请号：US870495
申请日：1997-06-06
申请人： Hiroaki Tanaka
发明人： Hiroaki Tanaka
IPC分类号： H03H9/145 , H03H7/07 , H03H9/02 , H03H9/05 , H03H9/64 , H03H11/06 , H03H9/52
CPC分类号： H03H9/64 , H03H9/0542 , H03H7/1708
摘要： An active filter includes a single resonator surface acoustic wave (SAW) filter with at least two ports, an amplifier, and a phase shifter. The SAW filter has at least two resonant modes which are combined to achieve characteristics of a multi-stage filter. The amplifier and the phase shifter are connected so as to compensate for insertion loss caused by the SAW filter.
摘要翻译：有源滤波器包括具有至少两个端口的单个谐振器表面声波（SAW）滤波器，放大器和移相器。 SAW滤波器具有至少两个谐振模式，其被组合以实现多级滤波器的特性。连接放大器和移相器，以补偿由SAW滤波器引起的插入损耗。

54. 发明授权

US5906645A Auto-drive control unit for vehicles 失效
标题翻译：车辆自动驾驶控制单元
公开(公告)号：US5906645A
公开(公告)日：1999-05-25
申请号：US743932
申请日：1996-11-05
申请人： Kazunori Kagawa , Hiroaki Tanaka
发明人： Kazunori Kagawa , Hiroaki Tanaka
IPC分类号： B60R21/00 , B60K31/00 , B60T7/12 , B60T7/22 , B60W30/00 , B62D1/28 , B62D6/00 , G05D1/02 , G06F7/70
CPC分类号： B60T7/12 , B60T7/22 , B60W50/12 , B62D1/28
摘要： A unit for smoothly switching from auto-drive to manual drive for a vehicle provided with an auto-drive mode. To perform auto-drive, an auto-drive ECU controls steering wheel, brake, and accelerator actuators in accordance with signals from a route recognition/obstruction check sensor, a GPS and the like. When an interface (switch) for switching to the manual drive is operated, the auto-drive ECU evaluates running stability/instability in accordance with signals from various running safety devices and sensors for detecting a variation in vehicle state, and if the vehicle is in an instable state, prohibits a shift to the manual drive, even when the vehicle is running on a straight road.
摘要翻译：用于自动驾驶模式的车辆的自动驾驶到手动驾驶的平滑切换的单元。为了执行自动驱动，自动驾驶ECU根据来自路线识别/障碍物检测传感器，GPS等的信号来控制方向盘，制动器和加速器执行器。当操作用于切换到手动驱动器的接口（开关）时，自动驾驶ECU根据来自各种运行的安全装置和用于检测车辆状态变化的传感器的信号来评估运行稳定性/不稳定性，并且如果车辆处于不稳定状态，即使当车辆在直路上行驶时，也禁止转向手动驱动。

55. 发明授权

US5877973A Logic operation circuit and carry look ahead adder 失效
标题翻译：逻辑运算电路并携带前瞻加法器
公开(公告)号：US5877973A
公开(公告)日：1999-03-02
申请号：US806213
申请日：1997-02-26
申请人： Koji Kato , Harutsugu Fukumoto , Hiroaki Tanaka
发明人： Koji Kato , Harutsugu Fukumoto , Hiroaki Tanaka
IPC分类号： G06F7/50 , G06F7/506 , G06F7/508
CPC分类号： G06F7/506 , G06F7/508
摘要： An 8-bit CLA adder is constructed for inputting 4 lower bits a3:0,b3:0 and 4 upper bits a7:4,b7:4 of two input signals to the two 4-bit full adders 2,12 and a carry c-1 to the lowest bit the full adder of the first-stage 2 to generate carries c3,c7 correspondint to the third and seventh bit of the input signals from a carry generation signal g7:0 and a carry propagation signal p7:0 generated by the both adders 2,12 and the carry c-1. The full adder of the second-stage 12 is constructed to add the 4 upper bits a7:4,b7:4 with setting a carry-in as 0 so as to generate a temporary summing signal sz7:4. A logical circuit 14 generates a true sum of 4 upper bits from a carry c3 to the third bit to the forth bit, a temporary sum sz7:4 and a carry propagation signal p7:4 generated by the full adder of the second-stage 12.
摘要翻译：一个8位CLA加法器被构造用于将两个输入信号的4个低位位a3：0，b3：0和4个高位位a7：4，b7：4输入到两个4位全加器2,12和一个进位c -1到第一级2的全加器的最低位，以产生载波c3，c7，对应于来自进位产生信号g7：0的输入信号的第三和第七位以及由...生成的进位传播信号p7：0 两个加法器2,12和进位c-1。第二级12的全加器被构造为通过将进位设置为0来添加4个高位位a7：4，b7：4，以产生临时求和信号sz7：4。逻辑电路14产生从进位c3到第三位到第四位的4个高位的真和，由第二级12的全加器产生的临时和sz7：4和进位传播信号p7：4 。

56. 发明授权

US5820486A Golf ball 失效
标题翻译：高尔夫球
公开(公告)号：US5820486A
公开(公告)日：1998-10-13
申请号：US687198
申请日：1996-07-25
申请人： Hiroaki Tanaka , Keiji Moriyama
发明人： Hiroaki Tanaka , Keiji Moriyama
IPC分类号： A63B37/00 , A63B37/12
CPC分类号： A63B37/12 , A63B37/0003 , A63B37/0031 , A63B37/0033 , A63B37/0037 , A63B37/0075 , Y10S273/06
摘要： A solid golf ball having a good shot feel and controllability as well as an excellent flight performance and durability which comprises a core and a cover covering the core, wherein the cover has a two layer structure composed of an outer cover and an inner cover, wherein the inner cover is prepared from a resin composition having a flexural modulus of 5,000 to 12,000 Kgf/cm.sup.2 and comprising a polyamide resin having a flexural modulus of 6,000 to 30,000 Kgf/cm.sup.2 with a thermoplastic elastomer having a JIS/A hardness of 30 to 98, in a weight ratio of polyamide: thermoplastic elastomer within the range of 95:5 to 50:50.
摘要翻译：具有良好的射击感和可控性的固体高尔夫球以及优异的飞行性能和耐久性，其包括芯和覆盖芯的盖，其中所述盖具有由外盖和内盖组成的两层结构，其中内盖由弯曲弹性模量为5000〜12,000Kgf / cm 2的树脂组合物制成，并且具有挠度为6,000〜30,000Kgf / cm 2的聚酰胺树脂，其热塑性弹性体的JIS / A硬度为30〜98 ，聚酰胺：热塑性弹性体的重量比在95:5至50:50的范围内。

57. 发明授权

US5812022A Differential amplifier circuit having low noise input transistors 失效
标题翻译：差分放大电路具有低噪声输入晶体管
公开(公告)号：US5812022A
公开(公告)日：1998-09-22
申请号：US715610
申请日：1996-09-18
申请人： Tetsuo Hirano , Ryuichirou Abe , Hiroaki Tanaka
发明人： Tetsuo Hirano , Ryuichirou Abe , Hiroaki Tanaka
IPC分类号： H03F1/26 , H03F3/45
CPC分类号： H03F3/45076
摘要： A differential amplifier circuit whose noise is reduced when used in a CMOS operational amplifier without increasing its cost includes a differential input stage circuit in which gate lengths of load transistors and gate lengths of differential input transistors are set to an optimal ratio to minimize internal transistor noise components.
摘要翻译：在不增加成本的情况下，在CMOS运算放大器中使用噪声降低的差分放大器电路包括差分输入级电路，其中负载晶体管的栅极长度和差分输入晶体管的栅极长度被设置为使最小化内部晶体管噪声的最佳比率组件。

58. 发明授权

US5771376A Pipeline arithmetic and logic system with clock control function for selectively supplying clock to a given unit 失效
标题翻译：具有时钟控制功能的管道算术和逻辑系统，用于选择性地为给定单元提供时钟
公开(公告)号：US5771376A
公开(公告)日：1998-06-23
申请号：US725495
申请日：1996-10-04
申请人： Hiroshi Hayakawa , Harutsugu Fukumoto , Hiroaki Tanaka
发明人： Hiroshi Hayakawa , Harutsugu Fukumoto , Hiroaki Tanaka
IPC分类号： G06F9/312 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/325 , G06F9/3867 , G06F9/3869
摘要： A pipeline arithmetic and logic system capable of adjusting operational timings among stages without using an NOP instruction, providing a size reduction of its control section. The system has a decoder set including decoder groups divided into a decoder group for controlling an arithmetic section unit, a register file unit and a program counter unit, and a decoder for control of an address unit, and further including a clock control unit controlled by the address unit control decoder. A clock signal from an external source is directly fed to the address unit while being fed through the clock control unit to the other units. When fetching a data transfer instruction and repeatedly executing an MA stage twice, the system stops the clock control unit at the execution of the first MA stage to inhibit the operations of the units other than the address unit.
摘要翻译：一种管道算术和逻辑系统，其能够在不使用NOP指令的情况下调整阶段之间的操作定时，从而提供其控制部分的尺寸减小。该系统具有解码器组，其包括被分成用于控制算术部分单元的解码器组，寄存器文件单元和程序计数器单元的解码器组，以及用于控制地址单元的解码器，还包括由地址单元控制解码器。来自外部源的时钟信号直接馈送到地址单元，同时通过时钟控制单元馈送到其它单元。当获取数据传输指令并重复执行MA阶段两次时，系统在执行第一MA级停止时钟控制单元以禁止地址单元以外的单元的操作。

59. 发明授权

US5727131A Neural network learning device 失效
标题翻译：神经网络学习装置
公开(公告)号：US5727131A
公开(公告)日：1998-03-10
申请号：US139710
申请日：1993-10-22
申请人： Joji Nakamura , Hiroaki Tanaka , Tomohisa Yoshimi , Takayoshi Kawai , Yuji Ito , Yuji Takeo
发明人： Joji Nakamura , Hiroaki Tanaka , Tomohisa Yoshimi , Takayoshi Kawai , Yuji Ito , Yuji Takeo
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/08 , G06N99/00 , G06E1/00 , G06E3/00
CPC分类号： G06N3/0454 , G06N3/08
摘要： A learning device that affects only the input-output relationships that should be additionally learned. A learning NN unit 8 capable of executing additional learning is provided separately from a learned NN unit 4 which is a basic control unit. The learned NN unit 4 produces a basic output in response to an input signal from a signal input unit 14, the learning NN unit 8 produces a correction amount desired by an individual person, and a desired control is performed based on the total value. When the output is changed, a difference is calculated between the changed output value and the basic output value from a first output unit 15, and the learning NN unit 8 executes the additional learning based upon the difference and the input value at this moment in compliance with a back-propagation method.
摘要翻译：仅影响应该额外学习的输入 - 输出关系的学习设备。与作为基本控制单元的学习NN单元4分开提供能够执行附加学习的学习NN单元8。所学习的NN单元4响应于来自信号输入单元14的输入信号产生基本输出，学习NN单元8产生个人期望的校正量，并且基于总值执行期望的控制。当输出改变时，在改变的输出值和来自第一输出单元15的基本输出值之间计算差值，并且学习NN单元8基于此时的差异和输入值执行附加学习具有反向传播方法。

60. 发明授权

US5717364A Mixer 失效
标题翻译：混合器
公开(公告)号：US5717364A
公开(公告)日：1998-02-10
申请号：US734468
申请日：1996-10-17
申请人： Mitsuo Ariie , Hiroaki Tanaka
发明人： Mitsuo Ariie , Hiroaki Tanaka
IPC分类号： H03D7/12 , H03D7/14 , H03B21/00 , H03C3/00 , H04B1/28
CPC分类号： H03D7/1441 , H03D7/125 , H03D7/1458 , H03D2200/0043 , H03D2200/0088 , H03D7/14
摘要： A small and inexpensive mixer that does not require a choke inductor and a large-capacitance capacitor. The mixer has a FET. The FET's source is grounded via a capacitor and is also connected to a power-supply terminal. The FET's gate is coupled to a bias voltage and also connected to a gate input terminal via a capacitor. The FET's drain is connected to an output terminal via a capacitor. A modulating signal is input into the power-supply terminal, and a local signal is input into the gate input terminal, so that a modulated signal is output from the output terminal.
摘要翻译：一种不需要扼流圈电感器和大容量电容器的小型廉价混频器。混频器有一个FET。 FET的源极通过电容器接地，并且还连接到电源端子。 FET的栅极耦合到偏置电压，并且还经由电容器连接到栅极输入端子。 FET的漏极通过电容器连接到输出端子。调制信号被输入到电源端子中，并且本地信号被输入到栅极输入端子中，从而从输出端子输出调制信号。

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