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51. 发明授权

US07692907B2 Circuit for electrostatic discharge (ESD) protection 有权
标题翻译：静电放电（ESD）保护电路
公开(公告)号：US07692907B2
公开(公告)日：2010-04-06
申请号：US11717948
申请日：2007-03-13
申请人： Shih-Hung Chen , Ming-Dou Ker
发明人： Shih-Hung Chen , Ming-Dou Ker
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04 , H02H3/22 , H01C7/12 , H02H1/00 , H02H1/04
CPC分类号： H01L27/0251 , H01L27/0292
摘要： A circuit capable of providing electrostatic discharge (ESD) protection, the circuit comprising a first set of power rails comprising a first high power rail and a first low power rail, a first interface circuit between the first set of power rails, the first interface circuit having at least one gate electrode, a first ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, and a second ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, the first ESD device and the second ESD device being configured to maintain a voltage level at the at least one gate electrode of the first interface circuit at approximately a ground level when ESD occurs.
摘要翻译：一种能够提供静电放电（ESD）保护的电路，所述电路包括包括第一高功率轨道和第一低功率轨道的第一组电力轨道，所述第一组电力轨道之间的第一接口电路，所述第一接口电路具有至少一个栅电极，第一ESD器件，其包括耦合到所述第一接口电路的所述至少一个栅电极的端子，以及包括耦合到所述第一接口电路的所述至少一个栅电极的端子的第二ESD器件，第一ESD器件和第二ESD器件被配置为当ESD发生时将第一接口电路的至少一个栅电极的电压电平保持在大致的接地电平。

52. 发明申请

US20090117763A1 CARD FIXER 有权
标题翻译：卡片固定器
公开(公告)号：US20090117763A1
公开(公告)日：2009-05-07
申请号：US12211062
申请日：2008-09-15
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01R13/44
CPC分类号： H05K5/0265 , H05K5/0282 , Y10S439/945
摘要： A card fixer is suitable to assist a card to be fixed in a slot of an electronic device. The card fixer includes a body and a clipping structure, wherein the body has a first side and a second side parallel to the first side. A hook is disposed on the first side of the body. The clipping structure extends out of the second side of the body for clipping the card thereon. When the clipping structure of the card fixer clips the card and the assembly of the card fixer with the card is inserted into the slot, the hook is locked on an inside wall of the slot.
摘要翻译：卡固定器适合于帮助卡固定在电子设备的槽中。卡定位器包括主体和夹持结构，其中主体具有平行于第一侧的第一侧和第二侧。钩体设置在身体的第一侧。剪辑结构从身体的第二侧延伸出来，以将卡夹在其上。当卡片固定器的剪辑结构夹住卡时，卡片固定器与卡的组合被插入到插槽中，钩被锁定在插槽的内壁上。

53. 发明申请

US20090020746A1 SELF-ALIGNED STRUCTURE AND METHOD FOR CONFINING A MELTING POINT IN A RESISTOR RANDOM ACCESS MEMORY 有权
标题翻译：自对准结构和方法，用于在电阻随机访问存储器中配置熔点
公开(公告)号：US20090020746A1
公开(公告)日：2009-01-22
申请号：US12235773
申请日：2008-09-23
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

54. 发明授权

US07414258B2 Spacer electrode small pin phase change memory RAM and manufacturing method 有权
标题翻译：间隔电极小针相变存储器RAM及制造方法
公开(公告)号：US07414258B2
公开(公告)日：2008-08-19
申请号：US11424123
申请日：2006-06-14
申请人： Hsiang Lan Lung , Shih-Hung Chen
发明人： Hsiang Lan Lung , Shih-Hung Chen
IPC分类号： H01L29/18
CPC分类号： H01L27/2436 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C2213/31 , G11C2213/79 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1675
摘要： A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.
摘要翻译：一种存储装置，包括具有顶侧的侧壁的第一盘形电极，具有顶侧的侧壁和在第一侧壁和第二侧壁之间的绝缘壁的第二盘形电极。绝缘壁在相应顶面附近的第一和第二侧壁之间具有厚度。记忆材料桥跨越绝缘壁，并且在绝缘壁之间限定第一和第二电极之间的电极间路径。提供这样的存储单元阵列。记忆材料的桥梁具有亚光刻尺寸。

55. 发明申请

US20080142984A1 Multi-Layer Electrode Structure 有权
标题翻译：多层电极结构
公开(公告)号：US20080142984A1
公开(公告)日：2008-06-19
申请号：US11611428
申请日：2006-12-15
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： An electrode structure including two parallel electrical paths. A plurality of electrode layers, generally tabular in form is formed in a stack, the outermost layers providing electrical contacts, and defining a first electrical current path through the stack. Two sidewall conductor layers are formed to abut either end of the electrode layer stack, two sidewall conductor layers defining a second electrical current path. The ends of the sidewall conduction layers lie in the same planes as the electrode layer electrical contacts, such that electrode structure electrical contacts are each formed from one set of sidewall layer ends and an electrode layer electrical contact.
摘要翻译：一种包括两个平行电路的电极结构。多个电极层通常以叠片的形式形成在堆叠中，最外层提供电触点，并且限定穿过叠层的第一电流路径。形成两个侧壁导体层以邻接电极层堆叠的任一端，限定第二电流路径的两个侧壁导体层。侧壁导电层的端部位于与电极层电接触相同的平面中，使得电极结构电触头各自由一组侧壁层端部和电极层电接触形成。

56. 发明申请

US20080121861A1 Self-Aligned Structure and Method for Confining a Melting Point in a Resistor Random Access Memory 有权
标题翻译：用于限制电阻随机存取存储器中的熔点的自对准结构和方法
公开(公告)号：US20080121861A1
公开(公告)日：2008-05-29
申请号：US11465094
申请日：2006-08-16
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

57. 发明申请

US20080062598A1 ESD PROTECTION CIRCUIT USING SELF-BIASED CURRENT TRIGGER TECHNIQUE AND PUMPING SOURCE MECHANISM 有权
标题翻译：使用自偏移电流触发技术和泵浦源机制的ESD保护电路
公开(公告)号：US20080062598A1
公开(公告)日：2008-03-13
申请号：US11740904
申请日：2007-04-26
申请人： Shih-Hung Chen , Ming-Dou Ker
发明人： Shih-Hung Chen , Ming-Dou Ker
IPC分类号： H02H9/04
CPC分类号： H01L27/0266
摘要： A circuit capable of providing electrostatic discharge (ESD) protection includes a first transistor including a first gate and a first source, the first gate being connected to a conductive pad, an impedance device between the first source and a first power rail capable of providing a resistor, a second transistor including a second gate and a second source, the second source being connected to the first power rail through the impedance device, and a clamp device between the first power rail and a second power rail, wherein the clamp device is capable of conducting a first portion of an ESD current and the second transistor is capable of conducting a second portion of the ESD current as the conductive pad is relatively grounded.
摘要翻译：能够提供静电放电（ESD）保护的电路包括：第一晶体管，包括第一栅极和第一源极，第一栅极连接到导电焊盘，第一源极与能够提供电阻器，包括第二栅极和第二源极的第二晶体管，所述第二源极通过所述阻抗器件连接到所述第一电力轨道，以及在所述第一电力轨道和第二电力轨道之间的夹紧装置，其中所述夹紧装置能够导电ESD电流的第一部分，并且当导电焊盘相对接地时，第二晶体管能够导通ESD电流的第二部分。

58. 发明申请

US20060126395A1 Non-volatile memory cell and operating method thereof 审中-公开
标题翻译：非易失性存储单元及其操作方法
公开(公告)号：US20060126395A1
公开(公告)日：2006-06-15
申请号：US11180093
申请日：2005-07-11
申请人： Shih-Hung Chen , Yi-Chou Chen
发明人： Shih-Hung Chen , Yi-Chou Chen
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C13/0004 , G11C13/003 , G11C2213/76
摘要： A non-volatile memory cell is provided. The non-volatile memory cell includes of a threshold switch material thin film and a memory switch material thin film, and the phases of the memory switch material layer is capable of changing. In addition, the memory switch material layer serves as a memory unit; the threshold switch material serves as a steering unit. Furthermore, the steering unit will breakdown when a voltage larger than its threshold voltage is provided, and the phase restores to the original state when the voltage is off.
摘要翻译：提供非易失性存储单元。非易失性存储单元包括阈值开关材料薄膜和存储器开关材料薄膜，并且存储器开关材料层的相位能够改变。此外，存储器开关材料层用作存储器单元; 阈值开关材料用作转向单元。此外，当提供大于其阈值电压的电压时，转向单元将击穿，并且当电压关闭时，相位恢复到原始状态。

59. 发明授权

US09048341B2 Integrated circuit capacitor and method 有权
标题翻译：集成电路电容及方法
公开(公告)号：US09048341B2
公开(公告)日：2015-06-02
申请号：US13451428
申请日：2012-04-19
申请人： Shih-Hung Chen , Kuang-Yeu Hsieh
发明人： Shih-Hung Chen , Kuang-Yeu Hsieh
IPC分类号： H01L21/02 , H01L49/02
CPC分类号： H01L28/91
摘要： An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.
摘要翻译：电容器的示例包括集成电路基板上的一系列脊和沟槽和互连区域。一系列脊和沟槽和互连区域具有在一系列脊和沟槽上具有蛇形横截面形状的电容器基座表面。电导体从互连区域电连接到电极层，用于进入电容器组件的电极层。

60. 发明授权

US09035275B2 Three dimensional memory array adjacent to trench sidewalls 有权
标题翻译：与沟槽侧壁相邻的三维存储器阵列
公开(公告)号：US09035275B2
公开(公告)日：2015-05-19
申请号：US13330525
申请日：2011-12-19
申请人： Wei-Chih Chien , Ming-Hsiu Lee , Shih-Hung Chen
发明人： Wei-Chih Chien , Ming-Hsiu Lee , Shih-Hung Chen
IPC分类号： H01L29/06 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1633
摘要： A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.
摘要翻译：一种自对准堆叠式存储单元阵列结构及其制造方法。存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

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