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51. 发明专利

JPH0290555A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0290555A
公开(公告)日：1990-03-30
申请号：JP24113588
申请日：1988-09-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MATSUGAMI SHOJI , OTSUKA KANJI , OKINAGA TAKAYUKI , OGUMA HIROSHI
IPC分类号： H01L23/36
摘要： PURPOSE:To dissipate efficiently heat generated from chips and to reduce the heat resistance of a package by a method wherein a cap is made to cover on a recessed part, in which the chips are sealed, on a pin grid array substrate and at the same time, a heat sink is connected to the outside of the cap and a gel is filled in the recessed part. CONSTITUTION:The interior of a recessed part 3 of a pin grid array substrate 1 is sealed with a cap 4 to cover the upper surface of the substrate 1. A heat sink 6 provided with heat dissipation fins 6a is bonded on the upper surface of the cap 4 using a bonding agent 6 for sealing use. A gel 13 having a high heat resistance and a high heat conductivity in combination is filled in a remaining region in the recessed part 3, in which a silicon wiring board 7 and chips 8 are sealed. Heat generated from the chips 8 is transferred to the sink 6 via CCB bumps 9, the board 7 and the cap 4, then, is dissipated from the surfaces of the fins 6a to the exterior. Moreover, the heat is transferred to the substrate 1 and input/output pins 2 via the gel 13. That is, as the ways of escape for the heat generated from the chips 8 are formed on both surfaces of the substrate 1, the heat dissipation efficiency of the chips is improved and the heat resistance of a package is reduced.

52. 发明专利

JPH0287556A SEALING JIG 失效
公开(公告)号：JPH0287556A
公开(公告)日：1990-03-28
申请号：JP23876488
申请日：1988-09-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OZAKI HIROSHI , OKINAGA TAKAYUKI , SHIRAI MASAYUKI , OTSUKA KANJI , AKASAKI HIROSHI
IPC分类号： H01L23/02
摘要： PURPOSE:To prevent the generation of blowholes by a method wherein a sealing jig is formed into a structure, wherein the constituent member of part of its main body is deformed due to its characteristics by heating, and is constituted in such a way that a pressing force is applied to a product pinched between pressing parts at a sealing temperature and the pressing force is released at a temperature lower than the sealing temperature. CONSTITUTION:If a sealing substrate 18 is inserted in a heating furnace, gas G is generated from a resin layer 8 adhered on the surface of a semiconductor pellet 7 on the condition of a comparatively low temperature of 100 deg.C or lower at the beginning of the insertion, but this gas is exhausted to the exterior from the contact part between a frame member 5 and a cap 12. If a heating is further increased and the heating temperature reaches the vicinity of a sealing temperature, a pressing force is applied between pressing pawls 15a and 15b due to a difference between the expansion coefficients of a clip main body 14 and a receiving member 16 and the member 5 and the cap 12 are brought in a closely adhered state. At this time, as most of the gas G is already exhausted to the exterior, the internal pressure in a cavity 4 is not increased, blowholes are never generated in a brazing metal 6, the member 5 and the cap 12 are closely adhered to each other and the hermetic seal of the cavity 4 is attained.

53. 发明专利

JPH01270238A WIRE BONDING ELEMENT 失效
公开(公告)号：JPH01270238A
公开(公告)日：1989-10-27
申请号：JP9813188
申请日：1988-04-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , OTSUKA KANJI , SHIRAI MASAYUKI , TATE HIROSHI , EMATA KOJI
IPC分类号： H01L21/60
摘要： PURPOSE:To prevent generation of shell-shaped cracks at an electrode pad so as to exclude adverse influences on the under of the pad by providing a shock absorbing layer to prevent bonding damage on almost central part of the surface of the electrode pad. CONSTITUTION:A shock absorbing layer 1 is provided at the central part of the surface of an electrode pad 2. And at the time of wire bonding, the ball part 6 of wire 5 for connector is pressed with a capillary 7 and bonded in the head shape of a nail on the pad 2 of a semiconductor chip 8 which has the electrode pad 2 where the shock absorbing layer 1 is formed at the central part of its surface. Accordingly, application of concentrated loads which occurs at the time of the first grounding when the ball part 6 is bonded by pressure to the surface of the pad 2 is diffused at the shock absorbing layer 1. Hereby, generation of shell-shaped cracks is prevented at the central part of the pad and adverse influences on the pad bed is excluded.

54. 发明专利

JPH01217993A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01217993A
公开(公告)日：1989-08-31
申请号：JP4205888
申请日：1988-02-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , OTSUKA KANJI , AKASAKI HIROSHI
IPC分类号： H01L23/50 , H01L23/057 , H01L23/498 , H05K1/18 , H05K3/30 , H05K3/34
摘要： PURPOSE:To eliminate positional deviation of a PGA easily and reliably, by forming some of lead pins of the PGA longer than the others, while providing holes in a packaging substrate on which the PGA is to be packaged so that the longer lead pins are inserted in the holes. CONSTITUTION:In order to package a PGA 2 face-to-face on the top face of a packaging substrate 1, solder paste is deposited on the surface of lands 10 formed on the top face of the packaging substrate 1, and the PGA 2 is put on the top face of the packaging substrate 1 while longer lead pins 9a at the four corners of the substrate 3 are inserted in holes 12 of the substrate 1. Thereby, the tip ends of the lead pins 9a are positioned correctly on the respective opposing lands 10 and fixed there temporarily. The packaging substrate 1 having the PGA 2 fixed temporarily is heated in a reflow furnace to melt the solder. Thereby, the lead pins 9 can be bonded to the respective lands 10 correctly without deviation.

55. 发明专利

JPH01135056A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01135056A
公开(公告)日：1989-05-26
申请号：JP29212087
申请日：1987-11-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIRAI MASAYUKI , UCHIUMI YASUYUKI , OTSUKA KANJI , OKINAGA TAKAYUKI , MATSUGAMI SHOJI
IPC分类号： H01L23/14 , H01L23/12 , H01L23/50
摘要： PURPOSE:To make it possible to readily correspond to the increase of input/output pins by composing a semiconductor device with a plurality of input/output pins which are detained at the rear of a wiring board without being exposed on the front side whereon a semiconductor integrated circuit element is mounted. CONSTITUTION:A through hole 5 of a large diameter which is formed in a secondary plate body 1b and one end of input/output pin is detained therein does not open to the upper surface of a primary plate body 1a whereon wiring structure 2 is formed. Therefore, the edge of an input/output pin 6 is not exposed on the upper surface of a primary plate body 1a, either. For instance, even if the number of input/output electrodes increases due to high integration of a semiconductor circuit device, and consequently the density of a plurality of wiring structures 2 formed on the upper surface of the primary plate body 1a is increased, it is not restricted to take around a plurality of wiring structures 2 in the upper surface of a primary plate body 1a by the bulge section of the input/output pin 6 exposed in the upper surface of the primary plate body 1a. In this way, it is possible to readily correspond to the increase of input/output electrodes at the semiconductor integrated circuit device 3, that is, increase of input/output pins 6.

56. 发明专利

JPH01135052A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01135052A
公开(公告)日：1989-05-26
申请号：JP29212187
申请日：1987-11-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIRAI MASAYUKI , UCHIUMI YASUYUKI , MATSUNAGA TOSHIHIRO , OTSUKA KANJI , OKINAGA TAKAYUKI
IPC分类号： H01L23/29 , H01L21/60 , H01L21/607 , H01L23/31
摘要： PURPOSE:To improve moisture resistance without developing thermal stress by composing a semiconductor device of a supporting member, a semiconductor element which is mounted thereon and whose surface is coated with a resin layer, and a bonding wire which connects the semiconductor element and the supporting member. CONSTITUTION:The surface of a semiconductor element 2 is coated with a resin layer 3 composed of silicone resin and the like. It is uniformly formed in a thickness about 10mum after applied with liquid resin, and then subjected to a heating and curing process. One end of a bonding wire 4 is connected to a connecting electrode 2c of the semiconductor element 2 by breaking through a resin layer 3 which covers the upper surface of the connecting electrode 2c this, and the other end is bonded to the side of a lead 1b thus electrically connecting a plurality of connecting electrodes 2c of the semiconductor element 2 and a plurality of leads 1b, respectively. Then sealing resin 5 is pressurized and filled in the inside of a die while the semiconductor element 2 which is mounted on a tab 1a of a lead frame 1 is contained in the die.

57. 发明专利

JPS6481333A TEST BOARD FOR FLIP-CHIP 失效
公开(公告)号：JPS6481333A
公开(公告)日：1989-03-27
申请号：JP23724587
申请日：1987-09-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , TATE HIROSHI , OTSUKA KANJI
IPC分类号： G01R1/067 , G01R31/26 , H01L21/66
摘要： PURPOSE:To stabilize a bump shape, to improve reliability and to form a test board for a flip-chip durable for repetition utility by not melting an electrode connected to the bump of the flip-chip with the bump, not diffusing it in an electrode pad, and composing it of conductive paste. CONSTITUTION:An electrode 2 for adhering the bump 5 of a flip-chip 6 in a test board 1 is composed of paste containing conductive substance, and the chip 6 is temporarily clamped by the electrode 2. Since the exfoliation of the chip 6 is conducted at the paste boundary of the electrode 2 when the chip 6 is removed from the board 1 after its evaluation test and the substance in the paste employs that which is not melted in the bump 5, the shape of the bump 5 is stabilized, and the deterioration of the reliability of the chip 6 can be avoided. Further, when the electrode 2 is formed in a shape for covering an Au pad 7 on the board 1, the diffusion of the Au pad 7 in the electrode 2 is suppressed, and the damage of the pad 7 is prevented.

58. 发明专利

JPS6454752A PIN GRID ARRAY SEMICONDUCTOR PACKAGE 失效
公开(公告)号：JPS6454752A
公开(公告)日：1989-03-02
申请号：JP21012487
申请日：1987-08-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： EMATA KOJI , MIYASHITA MASANORI , OKINAGA TAKAYUKI , SHIRAI MASAYUKI , OTSUKA KANJI
IPC分类号： H01L23/50 , H01L23/28
摘要： PURPOSE:To enhance the connecting strength of a lead frame and lead pins by providing a hole at the inner lead of a lead frame to stand the lead pins and forming a cutout in the hole. CONSTITUTION:A circular lead pin standing part 12 is formed on an inner lead 5, a pin insertion circular hole 10 is opened inside, and two cutouts 11 connected to the hole 10 are symmetrically formed at the outer parts of the hole 10. A metal pin 13 is inserted into the hole 10, stood on the lead 5, and head 13a protrudes from the surface of the inner lead. Then, the periphery of the hole 10 is raised upward to improve the connecting strength of the pin 13 to the inner lead, and not easily removed after sealing with resin. If necessary, the pin 13 is soldered at the periphery of the hole 10. After the pin 13 is stood on a lead frame 1, it is filled in a metal mold to transfer mold it, thereby completing a pin grid array package.

59. 发明专利

JPS6379361A UPRIGHT INSTALLATION TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6379361A
公开(公告)日：1988-04-09
申请号：JP22358186
申请日：1986-09-24
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： OKINAGA TAKAYUKI , TATE HIROSHI , OZAKI HIROSHI , SHIRAI MASAYUKI , OTSUKA KANJI
IPC分类号： H01L23/50 , H05K1/18 , H05K3/34 , H05K3/42
摘要： PURPOSE:To make through holes in a mounting substrate small, by uprightly installing the leads of the main body of a package so that the protruding surfaces of the leads face the surface of the mounting substrate, and by bonding and fixing the leads and the electrodes on the mounting substrate under the surface contact state. CONSTITUTION:Each outer lead 3 protrudes from a main body 2 of a package. The surface of the tip of each lead 3 is bonded to each electrode 3 of a mounting substrate 9. In this structure of a semiconductor device 1, each through hole 14, which is provided in the mounting substrate 9, is used only for conducting printed wirings 11 and 12. Therefore the diameter of each through hole 14 can be made small. The freedom of the layout of the printed wirings 11 and 12 on the upper and rear surfaces of the mounting substrate 9 can be improved. Since the electrodes 13 of the mounting substrate 9 and the outer leads 3 are conducted under the surface contact state, electric reliability of the semiconductor device 1 in the mounted state can be enhanced.

60. 发明专利

JPS6379350A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6379350A
公开(公告)日：1988-04-09
申请号：JP22357586
申请日：1986-09-24
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： MATSUGAMI SHOJI , OTSUKA KANJI , OKINAGA TAKAYUKI , SHIRAI MASAYUKI , TATE HIROSHI
IPC分类号： H01L23/12
摘要： PURPOSE:To decrease the warping of the base of a package, to promote the reduction in capacitance between wires and to shield external noises by grounding layers, by providing the grounding layer for an inner interconnection layer in addition to a grounding layer for a surface interconnection layer. CONSTITUTION:A surface interconnection layer 2 is provided on the surface of a base 1. A GND layer 3 is provided in the inside of the base 1. A plurality of lead pins 4 are extended in the vertical direction from the bottom surface of the base 1. An inner interconnection layer 5, by which the surface interconnection layer 2 and the lead pins 4 are connected, is formed in the base 1. The inner interconnection layer 5 comprises an interconnection part 5a, which is extended downward from the surface interconnection layer 2, an interconnection layer part 5b, which is provided in parallel with the GND layer 3, end an interconnection part 5c for connection. A GND layer 6 for the inner interconnection layer 5 is provided in parallel with the GND layer 3 at the bottom surface side of the base 1. The GND layers 3 and 6 are provided at upper and lower symmetrical positions with respect to a central line 7 crossing the base 1 so that balance is provided.

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