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51. 发明专利

JPS63142671A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63142671A
公开(公告)日：1988-06-15
申请号：JP28877386
申请日：1986-12-05
申请人： HITACHI LTD
发明人： INABA TORU , HAIJIMA MIKIO
IPC分类号： H01L29/73 , H01L21/331 , H01L27/06 , H01L29/72 , H01L29/732
摘要： PURPOSE:To prevent the generation of an excess current due to a short circuit of a load by a method wherein a high-concentration buried layer directly under an electrostatic-breakdown-preventive device is constructed at a region separated from another high-concentration buried layer directly under an input circuit in the same island region. CONSTITUTION:An electrostatic-breakdown-preventive device Q2 is composed of an n layer 1 and a p-layer 3; an electrode of the n layer 1 is connected to a bonding pad 5 as an input terminal via an Al wiring substrate 2; the other electrode of the n layer is short-circuited to the p-layer 3 and is connected to a base p-layer 12 of an npn transistor Q1 as an input circuit via an Al wiring part 4. A high-value resistor rc is situated at a part where an n buried layer 14 directly under the transistor Q1, as the input circuit, and an n buried layer 15 directly under the electrostatic- breakdown-preventive device Q2, both formed in the same island, are separated. Because this high-value resistor is equal to, or bigger than, the sum of the internal resistance value Rc of the transistor Q1, as the input circuit, and the internal resistance value of the device Q2, it is possible to prevent an excess current due to a short circuit of a load at the electrostatic-breakdown-preventive device. As a result, it is possible to prevent the excess current from flowing due to the short circuit of the load at the electrostatic-breakdown-preventive device and to secure a wiring part.

52. 发明专利

JPS6123356A Apparatus for preventing electrostatic breakdown of semiconductor device 失效
标题翻译：防止半导体器件静电破坏的装置
公开(公告)号：JPS6123356A
公开(公告)日：1986-01-31
申请号：JP14239484
申请日：1984-07-11
申请人： Akita Denshi Kk , Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： TAKIGAWA AKIRA , HAIJIMA MIKIO , IHARA HIROSHI , WATABE TOMOYUKI , WASHIO KATSUYOSHI , IWASAKI ISAO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0255
摘要： PURPOSE:To absorb both positive and negative surge pulses by forming an n type buried layer as a protection resistance and using a junction diode composed of the n type region and the p type diffused region. CONSTITUTION:When a forward surge pulse enters the electrode in the input terminal side, a voltage drops due to a resistance while a surge current flows into the n type buried layer 5. Thereby, an input voltage is clamped to a value which is equal to a breakdown voltage of the p-n junction diode D1 between the n type region 6a and p type region 9. Namely, holes are implanted to a low potential p type layer 9 from the n type region 6a, causing a current I1 to flow and absorbing a surge pulse. A backward surge current operates the p-n junction diode between the n type region 6a and the p type diffused layer 9 and an input voltage is clamped to a voltage (GND-VF) which is equal to a difference between the ground voltage and forward voltage VF of diode, causing electrons to be implanted to the side of p type diffused layer 9 from the n type region 6a.
摘要翻译：目的：通过形成n +型埋层作为保护电阻并使用由n +型区域和p型扩散区域构成的结二极管来吸收正和负浪涌脉冲。构成：当正向浪涌脉冲进入输入端侧的电极时，在浪涌电流流入n +型埋层5的同时由于电阻而下降，由此，将输入电压钳位到等于n +型区域6a和p型区域9之间的pn结二极管D1的击穿电压。即，从n +型区域6a将空穴注入到低电位p型层9中，导致电流I1流动并吸收浪涌脉冲。反向浪涌电流在n +型区域6a和p型扩散层9之间操作pn结二极管，并且将输入电压钳位到等于接地电压和二极管的正向电压VF，使电子从n +型区域6a注入到p型扩散层9侧。

53. 发明专利

JPS60152052A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60152052A
公开(公告)日：1985-08-10
申请号：JP709784
申请日：1984-01-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAIJIMA MIKIO , OGURA SADAO , KONDOU SHIZUO , WATABE TOMOYUKI , HAYASHI MAKOTO
IPC分类号： H01L21/8226 , H01L27/02 , H01L27/082
摘要： PURPOSE:To make each characteristic of an analog element and a digital element to coexist mutually without complicating processes by additionally doping a conductive impurity into a forming region for the digital element selectively. CONSTITUTION:An n type epitaxial layer 12 in comparatively low impurity concentration in an analog element forming region a1 is used as it is, thus forming an npn bipolar transistor Q1. On the other hand, an n type conductive impurity is additionally doped selectively into the n type epitaxial layer 12 in comparatively low concentration in a digital element forming region a2, thus forming an IIL. The effective impurity concentration of the layer 12 in the region a2 is increased relatively because an n type diffusion layer 20 is diffused additionally into the low-concentration n type epitaxial layer 12. Accordingly, each characteristic of an analog element and a digital element can be made to coexist and improved mutually without complicating processes.

54. 发明专利

JPS60109243A SEMICONDUCTOR IC DEVICE 失效
公开(公告)号：JPS60109243A
公开(公告)日：1985-06-14
申请号：JP21616083
申请日：1983-11-18
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , SHIMIZU ISAO
IPC分类号： H01L21/8222 , H01L21/331 , H01L21/76 , H01L21/764 , H01L27/082 , H01L29/73 , H01L29/732
摘要： PURPOSE:To contrive to improve the integration density by enabling the width of an isolation band to be narrowed by a method wherein a groove is dug between the forming region for a high withstand element and that for a logic element, and the isolation band is formed along this groove. CONSTITUTION:An Si semiconductor substrate 10 is doped with a p type conductivity impurity at low concentration. A semiconductor substrate formed by using the substrate 10 has an n Si epitaxial layer 12 doped with an n type conductivity type impurity at low concentration formed as a semiconductor layer on the surface of the p type substrate 10. The groove 21 is formed in the epitaxial layer along the parts dividing the element-forming regions, a1, a2, and a3. The epitaxial layer in the region a3 where the IIL is formed in cut off. Therey, only said layer in the region a3 is formed thinly. The isolation band produced by the groove and a p type diffused layer 30 is formed along the groove. The process of selective diffusion of a p type conductivity impurity at medium concentration is carried out. Electrode lead-out and wiring are performed from elements formed in the regions a1, a2, and a3 respectively by aluminum 50 and the like.

55. 发明专利

JPS6058654A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6058654A
公开(公告)日：1985-04-04
申请号：JP16663183
申请日：1983-09-12
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO
IPC分类号： H01L27/04 , H01L21/761 , H01L21/822 , H01L21/8222 , H01L27/082
摘要： PURPOSE:To obtain the titled device of the junction capcacitance per unit area by a method wherein an n type buried region is diffusion-formed in the surface layer part of a p type Si substrate, an n type layer epitaxially grown over the entire surface including the region, and the surface of the buried region being then exposed by boring a recess in the epitaxial layer, where a p type region and n type region are diffusion- formed, and a negative voltage and a positive voltage are inpressed on these regions, respectively. CONSTITUTION:The n type buried region 8 is diffusion-formed in the surface layer part of the p type Si substrate 1, the n type layer 2 being epitaxially grown over the entire surface including the region, and at the same time the upper part of the region 8 then being advanced into the layer 2 by the swelling of the volume of the region 8. Next, the surface of the region 8 is exposed by etching the layer 2 with SiO2 films 9 and 10 formed by methods of oxidation and CVD as a mask, and then the layers 2 is isolated in island form by means of a p type region 14 reaching the substrate 1, while containing the region 8. thereafter, the p type region 13 and the n type region 15 are provided in the region 8, the films 9 and 10 are removed, windows are opened after adhesion of an SiO2 film 16 over the entire surface, and electrodes A1 ans B1 for impressing negative and positive voltages are mounted on the regions 13 and 15, respectively.

56. 发明专利

JPS6058634A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6058634A
公开(公告)日：1985-04-04
申请号：JP16662783
申请日：1983-09-12
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , SHIMIZU ISAO
IPC分类号： H01L21/8226 , H01L21/331 , H01L21/761 , H01L27/082 , H01L29/73 , H01L29/732
摘要： PURPOSE:To improve characteristics of a logic element securing tension resistance of a high tension resisting element by making the thickness of a semiconductor layer for a logic element forming region thinner and the thickness of a semiconductor layer for a high tension resisting element forming region thicker when an IC provided with the high tension resisting element and the logic element on the same semiconductor substrate is formed. CONSTITUTION:In a part of a p type Si substrate 10, a recessed portion 20 of truncated pyramid shape, a region a1, is provided. In the region a1 and the adjacent regions a2 and a3, an n type buried region 14 is formed by diffusion respectively. Then, on all the surface, an n type layer 12 is grown epitaxially, a recessed portion 22 is provided on the surface corresponding to the region a3 where the thickness of the layer 12 is made thinner and the layer 12 is separated to an island state including the region 14 using a p type region 30. Later, a p type region 32 and a n type region 40 for connecting to a collector in the region a1, the p type region 32 in the region a2 and the p type region 32 in the region a3 is diffused respectively. The region a1 is used for a n-p-n type bipolar transistor for high tension resisting linear, the region a2 is used is used for a normal n-p-n type element and the region a3 is used for an I L element respectively.

57. 发明专利

JPS59217361A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59217361A
公开(公告)日：1984-12-07
申请号：JP9067083
申请日：1983-05-25
申请人： Hitachi Ltd
发明人： HAIJIMA MIKIO
IPC分类号： H01L29/872 , H01L21/28 , H01L29/47 , H01L29/73 , H01L29/48
CPC分类号： H01L29/7308
摘要： PURPOSE:To prevent the drop of forward directional voltage and the deterioration of withstand voltage by a method wherein contact alloy treatment with a substrate semiconductor is performed at the stage of a thin metallic film thickness by vapor-depositing Al or Si contained Al twice on the electrode metals of a low resistance contact electrode and a Schottky diode electrode. CONSTITUTION:After p type diffusion and n type diffusion, a part of the substrate and the p type layer and a part of the n type layer are exposed by contact-photoetching the SiO2 film 4 on the surface. Next, Al is vapor-deposited over the entire surface and heat-treated, thus forming a contact part 6 made of an Al-Si alloy layer at the interface between Si and Al. Then, after forming an Al (or Si contained Al) film 5b by evaporating Al (or Si contained Al) over the entire surface, it is lightly heat-treated to obtain low resistant contact. The unnecessary parts of the Al films 5a and 5b are removed, and then the Schottky diode electrode 9 is formed on one side, and the electrode 8 contacting the emitter in low resistance on the other side. This manner enables to obtain the low resistance contact electrode having no alloy bits by reducing the Al amount at the time of vapor deposition once. Accordingly, there is little Si deposition at the interface between the SBD electrode and Si, leading to no possibility of the drop of forward directional voltage.
摘要翻译：目的：为了防止正向定向电压的下降和耐电压的劣化，其中通过在薄金属膜厚度的阶段执行用基板半导体进行接触合金处理的方法，其中通过在Al 低电阻接触电极和肖特基二极管电极的电极金属。构成：在p型扩散和n +型扩散之后，通过对表面上的SiO 2膜4进行接触光刻，露出衬底和p型层的一部分和n +型层的一部分。接着，在整个表面上蒸镀Al并对其进行热处理，从而在Si和Al之间的界面处形成由Al-Si合金层构成的接触部6。然后，通过在整个表面上蒸发Al（或含有Al的Al）形成Al（或含Si的Al）膜5b之后，轻轻地进行热处理以获得低的耐接触性。除去Al膜5a和5b的不必要部分，然后在一侧形成肖特基二极管电极9，并且在另一侧上形成低电阻接触发射极的电极8。通过这样的方式，能够通过在蒸镀时减少Al量来获得不含合金的低电阻接触电极。因此，在SBD电极和Si之间的界面处存在很少的Si沉积，导致不存在向前定向电压下降的可能性。

58. 发明专利

JPS58106857A SWITCHING LOGIC CIRCUIT 失效
公开(公告)号：JPS58106857A
公开(公告)日：1983-06-25
申请号：JP20374381
申请日：1981-12-18
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO
IPC分类号： H01L21/8226 , H01L27/02 , H01L27/082 , H03K19/091
摘要： PURPOSE:To prevent the breakdown of semiconductor device itself while improving a margin to electrical noises and dielectric resistance to input signals by operating a switching element and an active element at the reference potential of potential higher than a grounding line. CONSTITUTION:When a transistor Q1 is driven in a saturation range, a P type base B and an N type collector C are forward-biassed. Consequently, currents flow, but the positive potential of +B is applied previously to the N type emitter E of the transistor Q2 of an I L circuit. Accordingly, a section between a P type base body and said N type emitter E is reverse-biassed. As a result, currents do not flow through a P-N junction between a P type element isolation region and the N type epitaxial growth layer of the transistor Q2 even when the P type base and the N type collector are forward-biassed. The reference potential of the I L circuit is made higher than the reference potentia of a linear circuit (not shown) only by voltage +B by applying the positive potential of +B.

59. 发明专利

JPS5793582A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5793582A
公开(公告)日：1982-06-10
申请号：JP16954680
申请日：1980-12-03
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO
IPC分类号： H01L29/93
摘要： PURPOSE:To obtain a specific capacitance change in a semiconductor device by forming a defect in the second semiconductor region, forming a junction with the existing first semiconductor region and communicating the third semiconductor region formed at the periphery of the defect with the first semiconductor region. CONSTITUTION:A defect 5 is formed in the second conductive type second semiconductor region 4, and a junction is formed with the existing first conductive type first semiconductor region 2. The first conductive type semiconductor region 6 formed in the second semiconductor region 4 is communicated at least around the periphery of the defect 5 with the first semiconductor region 2. Thus, it can obtain the specific junction capacitance change.

60. 发明专利

JPS56169358A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS56169358A
公开(公告)日：1981-12-26
申请号：JP7139980
申请日：1980-05-30
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO
IPC分类号： H01L29/78 , H01L21/331 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L29/73
摘要： PURPOSE:To improve the withstand voltage and the frequency characteristics of a semiconductor integrated circuit by providing a P type base in contact with an N type emitter, a P type well around the base and an N type power source connecting layer in contact with the well and employing a junction capacity between the emitter and the base. CONSTITUTION:An N type layer 2 is buried in a P type substrate 1, an N type epitaxial layer 3 is superposed thereon, a P type layer 48 is formed, and with an SiO2 film 42 as a mask a P type layer 41 is selectively injected with ions. The layers 48, 41 are diffused by a heat treatment, elements are isolated via isolators 8, and P type wells 31, 21 are formed. With SiO2 film 52 grown as mask a P type layer 4 is formed in the well 21. Thereafter, N type layers 36, 38 are formed in the well 31 and an N type layer 5 is simultaneously formed in the layer 4 in accorance with known method. According to this configuration, it can prevent a punch-through, can improve the withstand voltage without variation of capacity per unit area of the P-N junction, can expand the depletion layer width of the base and collector junction, can reduce the parasitic capacity with the power source, thereby obtaining an IC incorporating a capacitive element and an I L improved in its frequency characteristics in combination.

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