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51. 发明申请

US20130313513A1 SEMICONDUCTOR DEVICES HAVING MODULATED NANOWIRE COUNTS 审中-公开
标题翻译：具有调制纳米级数的半导体器件
公开(公告)号：US20130313513A1
公开(公告)日：2013-11-28
申请号：US13996505
申请日：2011-12-23
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Gopinath Bhimarasetti , Tahir Ghani , Seiyon Kim
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Gopinath Bhimarasetti , Tahir Ghani , Seiyon Kim
IPC分类号： H01L29/775 , H01L21/02 , H01L27/088
摘要： Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.
摘要翻译：描述了具有调制纳米线计数的半导体器件和形成这种器件的方法。例如，半导体结构包括具有多个纳米线的第一半导体器件，该多个纳米线设置在衬底上并且堆叠在具有第一最上层纳米线的第一垂直平面中。第二半导体器件具有设置在衬底上方的一个或多个纳米线并且堆叠在具有第二最上层纳米线的第二垂直平面中。第二半导体器件包括比第一半导体器件少的一个或多个纳米线。第一和第二最上层的纳米线设置在与第一和第二垂直平面正交的同一平面中。

52. 发明授权

US08198692B2 Spin torque magnetic integrated circuits and devices therefor 有权
标题翻译：自旋扭矩磁性集成电路及其设备
公开(公告)号：US08198692B2
公开(公告)日：2012-06-12
申请号：US13279112
申请日：2011-10-21
申请人： Dmitri E. Nikonov , George I. Bourianoff , Tahir Ghani
发明人： Dmitri E. Nikonov , George I. Bourianoff , Tahir Ghani
IPC分类号： H01L29/82 , G11C11/00
CPC分类号： H01L43/08 , B82Y25/00 , B82Y40/00 , G01R33/093 , G01R33/1284 , G11C11/161 , H01F10/133 , H01F10/3254 , H01F10/329 , H01F41/307 , H01L27/22 , H01L27/228 , H01L43/12
摘要： Spin torque magnetic integrated circuits and devices therefor are described. In an example, a spin torque magnetic device for a logic circuit includes a majority gate structure. An output is coupled to the majority gate structure. Three inputs are also coupled to the majority gate structure.
摘要翻译：描述了自旋扭矩磁集成电路及其装置。在一个示例中，用于逻辑电路的自旋扭矩磁性装置包括多数门结构。输出耦合到多数门结构。三个输入也耦合到多数门结构。

53. 发明申请

US20120038387A1 SPIN TORQUE MAGNETIC INTEGRATED CIRCUITS AND DEVICES THEREFOR 有权
公开(公告)号：US20120038387A1
公开(公告)日：2012-02-16
申请号：US13279112
申请日：2011-10-21
申请人： Dmitri E. Nikonov , George I. Bourianoff , Tahir Ghani
发明人： Dmitri E. Nikonov , George I. Bourianoff , Tahir Ghani
IPC分类号： H03K19/23
CPC分类号： H01L43/08 , B82Y25/00 , B82Y40/00 , G01R33/093 , G01R33/1284 , G11C11/161 , H01F10/133 , H01F10/3254 , H01F10/329 , H01F41/307 , H01L27/22 , H01L27/228 , H01L43/12
摘要： Spin torque magnetic integrated circuits and devices therefor are described. In an example, a spin torque magnetic device for a logic circuit includes a majority gate structure. An output is coupled to the majority gate structure. Three inputs are also coupled to the majority gate structure.

54. 发明授权

US08063460B2 Spin torque magnetic integrated circuits and devices therefor 有权
标题翻译：自旋扭矩磁性集成电路及其设备
公开(公告)号：US08063460B2
公开(公告)日：2011-11-22
申请号：US12642342
申请日：2009-12-18
申请人： Dmitri E. Nikonov , George I. Bourianoff , Tahir Ghani
发明人： Dmitri E. Nikonov , George I. Bourianoff , Tahir Ghani
IPC分类号： H01L29/82 , G11C11/00
CPC分类号： H01L43/08 , B82Y25/00 , B82Y40/00 , G01R33/093 , G01R33/1284 , G11C11/161 , H01F10/133 , H01F10/3254 , H01F10/329 , H01F41/307 , H01L27/22 , H01L27/228 , H01L43/12
摘要： Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer.
摘要翻译：描述了自旋扭矩磁集成电路及其装置。自旋扭矩磁集成电路包括设置在基板上方的第一自由铁磁层。非磁性层设置在第一自由铁磁层的上方。包括多个写柱和多个读柱，每个柱设置在非磁性层之上并且包括固定的铁磁层。

55. 发明授权

US06885084B2 Semiconductor transistor having a stressed channel 有权
公开(公告)号：US06885084B2
公开(公告)日：2005-04-26
申请号：US10626257
申请日：2003-07-23
申请人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
发明人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
IPC分类号： H01L21/336 , H01L29/10 , H01L29/165 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7842
摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

56. 发明授权

US06861318B2 Semiconductor transistor having a stressed channel 有权
标题翻译：具有应力通道的半导体晶体管
公开(公告)号：US06861318B2
公开(公告)日：2005-03-01
申请号：US10626365
申请日：2003-07-23
申请人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
发明人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
IPC分类号： H01L21/336 , H01L29/10 , H01L29/165 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7842
摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
摘要翻译：描述了用于制造改进的PMOS半导体晶体管的工艺。凹陷被蚀刻成一层外延硅。源极和漏极膜沉积在凹槽中。源极和漏极膜由硅和锗的合金制成。合金外延沉积在硅层上。合金因此具有与硅层的晶格结构相同结构的晶格。然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。应力增加晶体管的IDSAT和IDLIN。可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

57. 发明授权

US06271096B1 Method and device for improved salicide resistance on polysilicon gates 有权
标题翻译：在多晶硅闸门上提高耐化学性的方法和装置
公开(公告)号：US06271096B1
公开(公告)日：2001-08-07
申请号：US09458537
申请日：1999-12-09
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

58. 发明申请

US20190259699A1 INTEGRATED CIRCUIT DEVICE WITH BACK-SIDE INERCONNECTION TO DEEP SOURCE/DRAIN SEMICONDUCTOR 审中-公开
公开(公告)号：US20190259699A1
公开(公告)日：2019-08-22
申请号：US16348116
申请日：2016-12-23
申请人： Patrick Morrow , Mauro J. Kobrinsky , Mark T. Bohr , Tahir Ghani , Rishabh Mehandru
发明人： Patrick Morrow , Mauro J. Kobrinsky , Mark T. Bohr , Tahir Ghani , Rishabh Mehandru
IPC分类号： H01L23/528 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/66 , H01L29/40 , H01L21/306 , H01L27/088 , H01L27/02 , H01L21/8234
摘要： Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.

59. 发明申请

US20160284605A9 Methods for Fabricating Strained Gate-All-Around Semiconductor Devices by Fin Oxidation Using an Undercut Etch-Stop Layer 审中-公开
标题翻译：使用底切蚀刻停止层通过翅片氧化制造应变栅极全能半导体器件的方法
公开(公告)号：US20160284605A9
公开(公告)日：2016-09-29
申请号：US14266643
申请日：2014-04-30
申请人： Annalisa Cappellani , Abhijit Jayant Pethe , Tahir Ghani , Harry Gomez
发明人： Annalisa Cappellani , Abhijit Jayant Pethe , Tahir Ghani , Harry Gomez
IPC分类号： H01L21/84 , H01L29/423 , H01L29/06 , H01L29/08 , H01L21/306 , H01L29/66
CPC分类号： H01L29/42392 , B82Y10/00 , H01L21/30604 , H01L21/845 , H01L29/0649 , H01L29/0673 , H01L29/0847 , H01L29/401 , H01L29/41725 , H01L29/42356 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78696
摘要： Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
摘要翻译：描述了形成在全局或局部隔离的基板上的应变门全面半导体器件。例如，半导体器件包括半导体衬底。绝缘结构设置在半导体衬底之上。三维沟道区设置在绝缘结构的上方。源极和漏极区域设置在三维沟道区域的两侧和外延晶种层上。外延种子层由不同于三维沟道区的半导体材料构成，并且设置在绝缘结构上。栅极电极堆叠围绕三维沟道区域，其中设置在绝缘结构上并且横向邻近外延籽晶层的部分。

60. 发明授权

US09006069B2 Pulsed laser anneal process for transistors with partial melt of a raised source-drain 有权
标题翻译：脉冲激光退火工艺用于具有部分熔化的源极 - 漏极的晶体管
公开(公告)号：US09006069B2
公开(公告)日：2015-04-14
申请号：US13976822
申请日：2011-12-19
申请人： Jacob Jensen , Tahir Ghani , Mark Y. Liu , Harold Kennel , Robert James
发明人： Jacob Jensen , Tahir Ghani , Mark Y. Liu , Harold Kennel , Robert James
IPC分类号： H01L21/268 , H01L29/66 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/268 , H01L21/324 , H01L29/0847 , H01L29/1037 , H01L29/165 , H01L29/41783 , H01L29/66628 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.
摘要翻译：一种非平面晶体管，其包括设置在半导体鳍片的相对端上的部分熔融的凸起半导体源极/漏极，其间设置有栅极堆叠。升高的半导体源极/漏极包括在熔体深度之上的超激活掺杂剂区域和低于熔体深度的活化掺杂剂区域。超活化掺杂剂区域具有比活化的掺杂剂区域更高的活化掺杂剂浓度和/或具有在整个熔融区域中恒定的活化的掺杂剂浓度。翅片形成在基板上，并且半导体材料或半导体材料堆叠沉积在设置在沟道区域的相对侧上的翅片的区域上以形成升高的源极/漏极。进行脉冲激光退火以仅将融化的半导体材料的一部分熔化在熔体深度之上。

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