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51. 发明授权

US06312988B1 Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions 失效
标题翻译：形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构
公开(公告)号：US06312988B1
公开(公告)日：2001-11-06
申请号：US09389532
申请日：1999-09-02
申请人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
发明人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
IPC分类号： H01L218242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node. In yet another embodiment, a plurality of capacitor storage nodes are formed arranged in columns. A common cell electrode layer is formed over the plurality of capacitor storage nodes. Cell electrode layer material is removed from between the columns and isolates individual cell electrodes over individual respective capacitor storage nodes. After the removing of the cell electrode layer material, conductive material is formed over portions of remaining cell electrode material thereby placing some of the individual cell electrodes into electrical communication with one another.
摘要翻译：描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。在另一个实施例中，电容器存储节点形成为具有与其接合的最上表面和侧表面。在最大表面上形成保护帽，并且在侧表面和保护盖上形成电容器电介质层。在电容器存储节点的侧表面上形成电池电极层。在另一个实施例中，形成多列电容器存储节点。在多个电容器存储节点上形成公共电极电极层。从柱之间移除电极电极层材料，并在各个电容器存储节点上隔离各个电池电极。在除去电池电极层材料之后，在剩余的电池电极材料的部分上形成导电材料，从而使一些单个电池电极彼此电连通。

52. 发明授权

US06180508B2 Methods of fabricating buried digit lines and semiconductor devices including same 有权
标题翻译：制造埋地数字线的方法及包括其的半导体器件
公开(公告)号：US06180508B2
公开(公告)日：2001-01-30
申请号：US09388769
申请日：1999-09-02
申请人： Tyler A. Lowrey
发明人： Tyler A. Lowrey
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76838 , H01L27/105 , H01L27/1052 , H01L27/10811 , H01L27/10885 , H01L27/10888
摘要： A method of electrically linking the contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corresponding digit line and, therefore, protrudes somewhat over a surface of the semiconductor device. A layer of insulative material is disposed over the semiconductor device with the mask material being exposed therethrough. The mask material is then removed, leaving open cavities that include the trench and a strap region continuous with the trench and with a connect region of the corresponding digit line. Conductive material is disposed within the cavity and electrically isolated from conductive material disposed in adjacent cavities, which define conductive plugs or studs and conductive straps from the conductive material. These plugs or studs and straps provide an electrically conductive link between each contact of the semiconductor device and its corresponding digit line. Semiconductor devices that include features that have been fabricated in accordance with the method of the present invention are also within the scope of the present invention.
摘要翻译：将半导体器件的触点电连接到其对应的数字线的方法。该方法包括将一定量的掩模材料设置在暴露于触点的沟槽中。掩模还邻接相应数字线的导电元件的连接区域，因此在半导体器件的表面上略微突出。绝缘材料层设置在半导体器件上，掩模材料暴露在其中。然后去除掩模材料，留下包括沟槽的开放空腔和与沟槽连续的带区域以及相应数字线的连接区域。导电材料设置在空腔内并与设置在相邻空腔中的导电材料电绝缘，其从导电材料限定导电塞或螺栓和导电带。这些插头或螺柱和带在半导体器件的每个触点与其对应的数字线之间提供导电连接。包括根据本发明的方法制造的特征的半导体器件也在本发明的范围内。

53. 发明授权

US06171872B2 Method of monitoring a process of manufacturing a semiconductor wafer including hemispherical grain polysilicon 失效
标题翻译：监测制造包括半球形晶粒多晶硅的半导体晶片的工艺的方法
公开(公告)号：US06171872B2
公开(公告)日：2001-01-09
申请号：US09145490
申请日：1998-09-01
申请人： Tyler A. Lowrey , Klaus F. Schuegraf , Randhir P. S. Thakur
发明人： Tyler A. Lowrey , Klaus F. Schuegraf , Randhir P. S. Thakur
IPC分类号： H01L2100
CPC分类号： H01L22/20 , H01L22/12
摘要： A method of monitoring a process of manufacturing a semiconductor wafer including an area of hemispherical grain polysilicon, the method comprising providing a probe including a liquid conductor; and performing a capacitance-voltage measurement with the probe, using a quasi-static measurement method, to determine capacitance-voltage characteristics at the area of hemispherical grain polysilicon.
摘要翻译：一种监视半导体晶片制造工艺的方法，所述半导体晶片包括半球形晶粒多晶硅的区域，所述方法包括提供包括液体导体的探针; 并使用准静态测量方法用探头进行电容电压测量，以确定半球形晶粒多晶硅区域的电容 - 电压特性。

54. 发明授权

US6136637A Method of forming CMOS circuitry including patterning conductive material overlying field isolation oxide 失效
标题翻译：形成CMOS电路的方法，包括图案化覆盖场隔离氧化物的导电材料层
公开(公告)号：US6136637A
公开(公告)日：2000-10-24
申请号：US124560
申请日：1998-07-28
申请人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
发明人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
IPC分类号： H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L21/8238
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823475 , H01L27/1052 , H01L27/10894
摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug
摘要翻译：公开了一种用于形成CMOS DRAM电路的方法，其包括形成包括阵列NMOS区，外围NMOS区和外围PMOS区的衬底; 在阵列NMOS区域中形成一对绝缘和间隔开的栅极线; 在所述阵列NMOS区域中形成至少一个导电插塞，并跨越所述一对栅极线; 在阵列NMOS区域，外围NMOS和外围PMOS区域中的一对栅极线上形成阻挡层; 并且在外围PMOS区域中图案化和蚀刻以形成外围PMOS区域栅极线，包括去除PMOS外围区域中的一部分势垒层，并且使阻挡层材料留在导电插塞

55. 发明授权

US6004868A Method for CMOS well drive in a non-inert ambient 失效
公开(公告)号：US6004868A
公开(公告)日：1999-12-21
申请号：US587403
申请日：1996-01-17
申请人： J. Brett Rolfson , Tyler A. Lowrey , Fernando Gonzalez , W. Richard Barbour
发明人： J. Brett Rolfson , Tyler A. Lowrey , Fernando Gonzalez , W. Richard Barbour
IPC分类号： H01L21/225 , H01L21/8238 , H01L21/324
CPC分类号： H01L21/823892 , H01L21/2253
摘要： Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

56. 发明授权

US5909203A Architecture for isolating display grids in a field emission display 失效
标题翻译：用于在场发射显示屏中隔离显示网格的架构
公开(公告)号：US5909203A
公开(公告)日：1999-06-01
申请号：US957693
申请日：1997-10-24
申请人： Jim J. Browning , John K. Lee , Tyler A. Lowrey
发明人： Jim J. Browning , John K. Lee , Tyler A. Lowrey
IPC分类号： G09G3/22 , H04N5/70 , H04N17/04 , G09G3/10
CPC分类号： H04N5/70 , G09G3/22 , H04N17/04
摘要： The present invention teaches a field emission display ("FED") architecture for isolating display grids, wherein an FED has a plurality of pixels. Each of the pixels comprise at least two field emitter tips for displaying information to the pixel and a pixelator for driving the field emitter tips. Further, an isolated display grid is incorporated for each of the field emitter tips. Each display grids is coupled to a bus having a predetermined voltage by a link. In one embodiment of the present invention, the link can be disintegrated by internal or external means. In a second embodiment, the FED comprises a first and second bus, each of bus having a predetermined voltage, whereby a first isolated display grid is coupled to the first bus by a first link and a second isolated display grids is coupled to the second bus by a second link.
摘要翻译：本发明教导了用于隔离显示网格的场发射显示（“FED”）架构，其中FED具有多个像素。每个像素包括用于向像素显示信息的至少两个场发射器尖端和用于驱动场发射器尖端的像素化器。此外，为每个场发射器尖端并入有隔离的显示栅格。每个显示网格通过链路耦合到具有预定电压的总线。在本发明的一个实施例中，链接可以通过内部或外部手段分解。在第二实施例中，FED包括第一和第二总线，每个总线具有预定电压，由此第一隔离显示网格通过第一链路耦合到第一总线，并且第二隔离显示网格耦合到第二总线通过第二个链接。

57. 发明授权

US5811329A Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide 失效
公开(公告)号：US5811329A
公开(公告)日：1998-09-22
申请号：US655683
申请日：1996-06-03
申请人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
发明人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
IPC分类号： H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L21/8238
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823475 , H01L27/1052 , H01L27/10894
摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug.

58. 发明授权

US5754149A Architecture for isolating display grids in a field emission display 失效
公开(公告)号：US5754149A
公开(公告)日：1998-05-19
申请号：US543739
申请日：1995-10-16
申请人： Jim J. Browning , John K. Lee , Tyler A. Lowrey
发明人： Jim J. Browning , John K. Lee , Tyler A. Lowrey
IPC分类号： G09G3/00 , G09G3/20 , G09G3/22 , H01J31/12 , H04N5/70 , H04N17/04 , G09G3/10
CPC分类号： G09G3/006 , G09G3/22 , H01J31/127 , H04N5/70 , G09G2300/0809 , G09G3/2014 , H04N17/04
摘要： The present invention teaches a field emission display ("FED") architecture for isolating display grids, wherein an FED has a plurality of pixels. Each of the pixels comprise at least two field emitter tips for displaying information to the pixel and a pixelator for driving the field emitter tips. Further, an isolated display grid is incorporated for each of the field emitter tips. Each display grids is coupled to a bus having a predetermined voltage by a link. In one embodiment of the present invention, the link can be disintegrated by internal or external means. In a second embodiment, the FED comprises a first and second bus, each of bus having a predetermined voltage, whereby a first isolated display grid is coupled to the first bus by a first link and a second isolated display grids is coupled to the second bus by a second link.

59. 发明授权

US5541872A Folded bit line ferroelectric memory device 失效
标题翻译：折叠位线铁电存储器件
公开(公告)号：US5541872A
公开(公告)日：1996-07-30
申请号：US450916
申请日：1995-05-26
申请人： Tyler A. Lowrey , Wayne I. Kinney
发明人： Tyler A. Lowrey , Wayne I. Kinney
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit. Thus, when the first and second word line reference transistors turn on, the bit line reference voltage is raised above ground potential by the sum of the voltages of the first and second ferroelectric capacitors. This in turn causes the bit line reference voltage, BL, to track the voltage variations of the ferroelectric capacitors in the main memory circuit, thus providing improved margins for the BL and BL complementary signals which are sensed by a plurality of sense amplifiers for the main memory circuit.
摘要翻译：这里描述了一种参考电压电路，其组合包括连接到位线的位线和第一和第二字线参考晶体管，并且可操作地与基准脉冲导通，同时在主存电路。第一和第二铁电电容器分别连接到第一和第二字线参考晶体管中的每一个以及板线切换电压源，并且第一预充电晶体管连接在第一铁电电容器和地电位之间。第二预充电晶体管连接在第二铁电电容器和另一开关电压源之间，使得第一和第二铁电电容器以与主电容器中的铁电电容器的逻辑状态相同的方式以一个和第零个状态极化铁电存储电路。因此，当第一和第二字线参考晶体管导通时，位线参考电压通过第一和第二铁电电容器的电压之和而升高到地电位以上。这又导致位线参考电压+ E，ovs BL + EE跟踪主存储器电路中的铁电电容器的电压变化，从而为BL和+ E，ovs BL + EE互补信号提供改善的余量其由用于主存储器电路的多个读出放大器感测。

60. 发明授权

US5424975A Reference circuit for a non-volatile ferroelectric memory 失效
标题翻译：非易失性铁电存储器的参考电路
公开(公告)号：US5424975A
公开(公告)日：1995-06-13
申请号：US175923
申请日：1993-12-30
申请人： Tyler A. Lowrey , Wayne I. Kinney
发明人： Tyler A. Lowrey , Wayne I. Kinney
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit. Thus, when the first and second word line reference transistors turn on, the bit line reference voltage is raised above ground potential by the sum of the voltages of the first and second ferroelectric capacitors. This in turn causes the bit line reference voltage, BL, to track the voltage variations of the ferroelectric capacitors in the main memory circuit, thus providing improved margins for the BL and BL complementary signals which are sensed by a plurality of sense amplifiers for the main memory circuit.
摘要翻译：这里描述了一种参考电压电路，其组合包括连接到位线的位线和第一和第二字线参考晶体管，并且可操作地与基准脉冲导通，同时在主存电路。第一和第二铁电电容器分别连接到第一和第二字线参考晶体管中的每一个以及板线切换电压源，并且第一预充电晶体管连接在第一铁电电容器和地电位之间。第二预充电晶体管连接在第二铁电电容器和另一开关电压源之间，使得第一和第二铁电电容器以与主电容器中的铁电电容器的逻辑状态相同的方式以一个和第零个状态极化铁电存储电路。因此，当第一和第二字线参考晶体管导通时，位线参考电压通过第一和第二铁电电容器的电压之和而升高到地电位以上。这又导致位线参考电压＆upbar＆B跟踪主存储器电路中的铁电电容器的电压变化，从而为由多个读出放大器感测的BL和＆amp; B和B互补信号提供改进的余量，主存储电路。

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