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1. 发明授权

US5923977A Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide 失效
标题翻译：形成CMOS电路的方法，包括图案化覆盖场隔离氧化物的导电材料层
公开(公告)号：US5923977A
公开(公告)日：1999-07-13
申请号：US970347
申请日：1997-11-14
申请人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
发明人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
IPC分类号： H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823475 , H01L27/1052 , H01L27/10894
摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug.
摘要翻译：公开了一种用于形成CMOS DRAM电路的方法，其包括形成包括阵列NMOS区，外围NMOS区和外围PMOS区的衬底; 在阵列NMOS区域中形成一对绝缘和间隔开的栅极线; 在所述阵列NMOS区域中形成至少一个导电插塞，并跨越所述一对栅极线; 在阵列NMOS区域，外围NMOS和外围PMOS区域中的一对栅极线上形成阻挡层; 以及在外围PMOS区域中图案化和蚀刻以形成外围PMOS区栅极线，包括去除PMOS外围区域中的一部分势垒层，并且使NMOS区域中的阻挡层材料掩蔽在导电插塞上。

2. 发明授权

US6136637A Method of forming CMOS circuitry including patterning conductive material overlying field isolation oxide 失效
标题翻译：形成CMOS电路的方法，包括图案化覆盖场隔离氧化物的导电材料层
公开(公告)号：US6136637A
公开(公告)日：2000-10-24
申请号：US124560
申请日：1998-07-28
申请人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
发明人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
IPC分类号： H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L21/8238
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823475 , H01L27/1052 , H01L27/10894
摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug
摘要翻译：公开了一种用于形成CMOS DRAM电路的方法，其包括形成包括阵列NMOS区，外围NMOS区和外围PMOS区的衬底; 在阵列NMOS区域中形成一对绝缘和间隔开的栅极线; 在所述阵列NMOS区域中形成至少一个导电插塞，并跨越所述一对栅极线; 在阵列NMOS区域，外围NMOS和外围PMOS区域中的一对栅极线上形成阻挡层; 并且在外围PMOS区域中图案化和蚀刻以形成外围PMOS区域栅极线，包括去除PMOS外围区域中的一部分势垒层，并且使阻挡层材料留在导电插塞

3. 发明授权

US5811329A Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide 失效
公开(公告)号：US5811329A
公开(公告)日：1998-09-22
申请号：US655683
申请日：1996-06-03
申请人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
发明人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
IPC分类号： H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L21/8238
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823475 , H01L27/1052 , H01L27/10894
摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug.

4. 发明授权

US06346439B1 Semiconductor transistor devices and methods for forming semiconductor transistor devices 失效
标题翻译：半导体晶体管器件和用于形成半导体晶体管器件的方法
公开(公告)号：US06346439B1
公开(公告)日：2002-02-12
申请号：US08677266
申请日：1996-07-09
申请人： Aftab Ahmad , David J. Keller
发明人： Aftab Ahmad , David J. Keller
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.
摘要翻译：本发明包括一种用于形成渐变连接区域的方法，包括：a）提供半导体材料晶片; b）在所述半导体材料晶片上提供晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）提供与所述晶体管栅极的侧壁相邻的侧壁间隔件，所述侧壁间隔件具有横向厚度; d）减小侧壁间隔物的横向厚度; 以及e）在减小所述侧壁间隔物的横向厚度之后，将导电性增强掺杂剂注入到所述半导体材料中以形成与所述晶体管栅极可操作地相邻的渐变连接区域。本发明还包括半导体晶体管器件，其包括：a）半导体材料晶片的区域; b）在所述半导体材料晶片的所述区域的一部分上的晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）与所述晶体管栅极可操作地相邻的源极/漏极区域，每个源极/漏极区域具有内侧边界; d）与晶体管栅极的侧壁相邻的相对的侧壁间隔件，每个侧壁间隔件具有外侧边缘，所述侧壁间隔件和源极/漏极区域成对，使得侧壁间隔件的外侧边缘相对于内侧源极/漏极区域的横向边界; 以及e）横向间隙，所述侧向间隙从所述侧壁间隔物的外侧边缘延伸到所述源极/漏极区域的内侧边界。

5. 发明授权

US06552394B2 Semiconductor transistor devices and structures with halo regions 有权
标题翻译：半导体晶体管器件和具有晕圈的结构
公开(公告)号：US06552394B2
公开(公告)日：2003-04-22
申请号：US09998420
申请日：2001-11-29
申请人： Aftab Ahmad , David J. Keller
发明人： Aftab Ahmad , David J. Keller
IPC分类号： H01L2976
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： The invention encompasses a transistor device comprising a region of a semiconductor material, and a transistor gate over a portion of the region. The device comprises a pair of opposing sidewall spacers adjacent sidewalls of the transistor gate and a pair of opposing first conductivity type source/drain regions within the semiconductor material proximate the transistor gate. The entirety of the semiconductor material under one of the sidewall spacers being defined as a first segment, and the entirety of the semiconductor material which is under the other of the sidewall spacers being defined as a second segment. The first and second segments of the semiconductor material are separated from the first and second source/drain regions by first and second gap regions, respectively, of the semiconductor material. The device further comprises a pair of opposing second conductivity type halo regions within the first and second gap regions.
摘要翻译：本发明包括一种包括半导体材料的区域的晶体管器件以及该区域的一部分上的晶体管栅极。该器件包括邻近晶体管栅极的一对相对的侧壁间隔件和邻近晶体管栅极的半导体材料内的一对相对的第一导电类型源/漏区。在一个侧壁间隔物之下的半导体材料的整体被定义为第一段，并且位于另一个侧壁间隔物之下的半导体材料的整体被定义为第二段。半导体材料的第一和第二段分别由半导体材料的第一和第二间隙区域与第一和第二源极/漏极区分离。该装置还包括在第一和第二间隙区域内的一对相对的第二导电类型的晕圈区域。

6. 发明授权

US06319779B1 Semiconductor transistor devices and methods for forming semiconductor transistor devices 失效
标题翻译：半导体晶体管器件和用于形成半导体晶体管器件的方法
公开(公告)号：US06319779B1
公开(公告)日：2001-11-20
申请号：US09167175
申请日：1998-10-06
申请人： Aftab Ahmad , David J. Keller
发明人： Aftab Ahmad , David J. Keller
IPC分类号： H01L218234
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.
摘要翻译：本发明包括一种用于形成渐变连接区域的方法，包括：a）提供半导体材料晶片; b）在所述半导体材料晶片上提供晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）提供与所述晶体管栅极的侧壁相邻的侧壁间隔件，所述侧壁间隔件具有横向厚度; d）减小侧壁间隔物的横向厚度; 以及e）在减小所述侧壁间隔物的横向厚度之后，将导电性增强掺杂剂注入到所述半导体材料中以形成与所述晶体管栅极可操作地相邻的渐变连接区域。本发明还包括半导体晶体管器件，其包括：a）半导体材料晶片的区域; b）在所述半导体材料晶片的所述区域的一部分上的晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）与所述晶体管栅极可操作地相邻的源极/漏极区域，每个源极/漏极区域具有内侧边界; d）与晶体管栅极的侧壁相邻的相对的侧壁间隔件，每个侧壁间隔件具有外侧边缘，所述侧壁间隔件和源极/漏极区域成对，使得侧壁间隔件的外侧边缘相对于内侧源极/漏极区域的横向边界; 以及e）横向间隙，所述侧向间隙从侧壁间隔件的外侧边缘延伸到源极/漏极区域的内侧边界。

7. 发明授权

US6165827A Semiconductor transistor devices and methods for forming semiconductor transistor devices 有权
公开(公告)号：US6165827A
公开(公告)日：2000-12-26
申请号：US167312
申请日：1998-10-06
申请人： Aftab Ahmad , David J. Keller
发明人： Aftab Ahmad , David J. Keller
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.

8. 发明授权

US06333539B1 Semiconductor transistor devices and methods for forming semiconductor transistor devices 失效
标题翻译：半导体晶体管器件和用于形成半导体晶体管器件的方法
公开(公告)号：US06333539B1
公开(公告)日：2001-12-25
申请号：US09167174
申请日：1998-10-06
申请人： Aftab Ahmad , David J. Keller
发明人： Aftab Ahmad , David J. Keller
IPC分类号： H01L2976
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： In one aspect, the invention encompasses a transistor device comprising a region of a semiconductor material wafer, and a transistor gate over a portion of the region. The transistor gate has a pair of opposing sidewalls which are a first sidewall and a second sidewall. The device further comprises a pair of opposing sidewall spacers adjacent the sidewalls of the transistor gate and a pair of opposing first conductivity type source/drain regions within the semiconductor material wafer proximate the transistor gate. One of the sidewall spacers extends along the first sidewall of the gate and the other of the sidewall spacers extends along the second sidewall of the gate. The entirety of the semiconductor wafer material under one of the sidewall spacers being defined as a first segment of the semiconductor wafer material, and the entirety of the semiconductor wafer material which is under the other of the sidewall spacers being defined as a second segment of the semiconductor wafer material. The first and second segments of the semiconductor material wafer are separated from the first and second source/drain regions by first and second gap regions, respectively, of the semiconductor material wafer. The device further comprises a pair of opposing second conductivity type halo regions within the first and second gap regions.
摘要翻译：在一个方面，本发明包括一种晶体管器件，其包括半导体材料晶片的区域和该区域的一部分上的晶体管栅极。晶体管栅极具有一对相对的侧壁，它们是第一侧壁和第二侧壁。该器件还包括邻近晶体管栅极的侧壁的一对相对的侧壁间隔物和靠近晶体管栅极的半导体材料晶片内的一对相对的第一导电类型源极/漏极区域。侧壁间隔件中的一个沿着栅极的第一侧壁延伸，并且另一个侧壁间隔件沿着栅极的第二侧壁延伸。将侧壁间隔物之一的半导体晶片材料的整体定义为半导体晶片材料的第一段，并且位于另一侧壁间隔物之下的整个半导体晶片材料被定义为第二段半导体晶片材料。半导体材料晶片的第一和第二段分别由半导体材料晶片的第一和第二间隙区域与第一和第二源极/漏极区分离。该装置还包括在第一和第二间隙区域内的一对相对的第二导电类型的晕圈区域。

9. 发明授权

US08367303B2 Semiconductor device fabrication and dry develop process suitable for critical dimension tunability and profile control 有权
标题翻译：半导体器件制造和干式开发工艺适用于关键尺寸可调性和型材控制
公开(公告)号：US08367303B2
公开(公告)日：2013-02-05
申请号：US11487246
申请日：2006-07-14
申请人： David J. Keller , Alex Schrinsky
发明人： David J. Keller , Alex Schrinsky
IPC分类号： G03F7/26
CPC分类号： H01L21/31122 , G03F1/00 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： The critical dimension (CD) of features formed during the fabrication of a semiconductor device may be controlled through the use of a dry develop chemistry comprising O2, SO2 and a hydrogen halide. For example, a dry develop chemistry comprising a gas comprising O2 and a gas comprising SO2 and a gas comprising HBr may be used to remove exposed areas of a carbon-based mask. The addition of HBr to the conventional O2 and SO2 dry develop chemistry enables a user to tune the critical dimension by growing, trimming and/or sloping the sidewalls and to enhance sidewall passivation and reduce sidewall bowing.
摘要翻译：在制造半导体器件期间形成的特征的临界尺寸（CD）可以通过使用包含O 2，SO 2和卤化氢的干式显影化学品来控制。例如，包括包含O 2的气体和包含SO 2的气体和包含HBr的气体的干式显影化学物质可用于除去碳基掩模的暴露区域。向传统的O2和SO2干式开发化学物质中添加HBr可使用户通过增长，修整和/或倾斜侧壁来调节临界尺寸，并增强侧壁钝化并减少侧壁弯曲。

10. 发明申请

US20090209072A1 Methods Of Forming Transistor Gates, Methods Of Forming Memory Cells, And Methods Of Forming DRAM Arrays 有权
标题翻译：形成晶体管栅极的方法，形成存储单元的方法和形成DRAM阵列的方法
公开(公告)号：US20090209072A1
公开(公告)日：2009-08-20
申请号：US12031015
申请日：2008-02-14
申请人： David J. Keller
发明人： David J. Keller
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/28
CPC分类号： H01L27/10873 , H01L21/28061 , H01L21/28247 , H01L21/28255 , H01L29/42368
摘要： Some embodiments include methods of forming transistor gates. A gate stack is placed within a reaction chamber and subjected to at least two etches, and to one or more depositions to form a transistor gate. The transistor gate may comprise at least one electrically conductive layer over a semiconductor material-containing layer. At least one of the one or more depositions may form protective material. The protective material may extend entirely across the at least one electrically conductive layer, and only partially across the semiconductor material-containing layer to leave unlined portions of the semiconductor material-containing layer. The unlined portions of the semiconductor material-containing layer may be subsequently oxidized.
摘要翻译：一些实施例包括形成晶体管栅极的方法。将栅极堆叠放置在反应室内并经历至少两个蚀刻，并进行一个或多个沉积以形成晶体管栅极。晶体管栅极可以包括含半导体材料的层上的至少一个导电层。一个或多个沉积中的至少一个可以形成保护材料。保护材料可以完全延伸穿过至少一个导电层，并且仅部分地横跨含半导体材料的层，以留下含半导体材料的层的无衬里部分。半导体材料含有层的无衬里部分可随后被氧化。

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