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1. 发明授权

US5541872A Folded bit line ferroelectric memory device 失效
标题翻译：折叠位线铁电存储器件
公开(公告)号：US5541872A
公开(公告)日：1996-07-30
申请号：US450916
申请日：1995-05-26
申请人： Tyler A. Lowrey , Wayne I. Kinney
发明人： Tyler A. Lowrey , Wayne I. Kinney
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit. Thus, when the first and second word line reference transistors turn on, the bit line reference voltage is raised above ground potential by the sum of the voltages of the first and second ferroelectric capacitors. This in turn causes the bit line reference voltage, BL, to track the voltage variations of the ferroelectric capacitors in the main memory circuit, thus providing improved margins for the BL and BL complementary signals which are sensed by a plurality of sense amplifiers for the main memory circuit.
摘要翻译：这里描述了一种参考电压电路，其组合包括连接到位线的位线和第一和第二字线参考晶体管，并且可操作地与基准脉冲导通，同时在主存电路。第一和第二铁电电容器分别连接到第一和第二字线参考晶体管中的每一个以及板线切换电压源，并且第一预充电晶体管连接在第一铁电电容器和地电位之间。第二预充电晶体管连接在第二铁电电容器和另一开关电压源之间，使得第一和第二铁电电容器以与主电容器中的铁电电容器的逻辑状态相同的方式以一个和第零个状态极化铁电存储电路。因此，当第一和第二字线参考晶体管导通时，位线参考电压通过第一和第二铁电电容器的电压之和而升高到地电位以上。这又导致位线参考电压+ E，ovs BL + EE跟踪主存储器电路中的铁电电容器的电压变化，从而为BL和+ E，ovs BL + EE互补信号提供改善的余量其由用于主存储器电路的多个读出放大器感测。

2. 发明授权

US5424975A Reference circuit for a non-volatile ferroelectric memory 失效
标题翻译：非易失性铁电存储器的参考电路
公开(公告)号：US5424975A
公开(公告)日：1995-06-13
申请号：US175923
申请日：1993-12-30
申请人： Tyler A. Lowrey , Wayne I. Kinney
发明人： Tyler A. Lowrey , Wayne I. Kinney
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit. Thus, when the first and second word line reference transistors turn on, the bit line reference voltage is raised above ground potential by the sum of the voltages of the first and second ferroelectric capacitors. This in turn causes the bit line reference voltage, BL, to track the voltage variations of the ferroelectric capacitors in the main memory circuit, thus providing improved margins for the BL and BL complementary signals which are sensed by a plurality of sense amplifiers for the main memory circuit.
摘要翻译：这里描述了一种参考电压电路，其组合包括连接到位线的位线和第一和第二字线参考晶体管，并且可操作地与基准脉冲导通，同时在主存电路。第一和第二铁电电容器分别连接到第一和第二字线参考晶体管中的每一个以及板线切换电压源，并且第一预充电晶体管连接在第一铁电电容器和地电位之间。第二预充电晶体管连接在第二铁电电容器和另一开关电压源之间，使得第一和第二铁电电容器以与主电容器中的铁电电容器的逻辑状态相同的方式以一个和第零个状态极化铁电存储电路。因此，当第一和第二字线参考晶体管导通时，位线参考电压通过第一和第二铁电电容器的电压之和而升高到地电位以上。这又导致位线参考电压＆upbar＆B跟踪主存储器电路中的铁电电容器的电压变化，从而为由多个读出放大器感测的BL和＆amp; B和B互补信号提供改进的余量，主存储电路。

3. 发明申请

US20090298224A1 Memory and Access Device and Method Therefor 有权
标题翻译：内存和访问设备及其方法
公开(公告)号：US20090298224A1
公开(公告)日：2009-12-03
申请号：US12538904
申请日：2009-08-11
申请人： Tyler A. Lowrey
发明人： Tyler A. Lowrey
IPC分类号： H01L21/06
CPC分类号： H01L27/2427 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1675
摘要： Briefly, in accordance with an embodiment of the invention, a memory and a method to manufacture the memory is provided. The memory may include a phase change material over a substrate. The memory may further include a switching material coupled to the phase change material, wherein the switching material comprises a chalcogen other than oxygen and wherein the switching material and the phase change material form portions of a vertical structure over the substrate.
摘要翻译：简而言之，根据本发明的实施例，提供了一种用于制造存储器的存储器和方法。存储器可以包括在衬底上的相变材料。存储器还可以包括耦合到相变材料的开关材料，其中开关材料包括除氧以外的硫族元素，并且其中开关材料和相变材料在衬底上形成垂直结构的部分。

4. 发明授权

US07563666B2 Semiconductor structures including vertical diode structures and methods of making the same 失效
标题翻译：包括垂直二极管结构的半导体结构及其制造方法
公开(公告)号：US07563666B2
公开(公告)日：2009-07-21
申请号：US11869012
申请日：2007-10-09
申请人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
发明人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
IPC分类号： H01L21/8234
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L27/0814 , H01L27/101 , H01L27/1021 , H01L27/24 , H01L29/6609 , H01L29/66136 , H01L29/861 , H01L45/04 , H01L45/145 , Y10S257/903 , Y10S257/91 , Y10S438/979
摘要： Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
摘要翻译：提供了制造垂直二极管结构的半导体结构和方法。垂直二极管结构可以具有延伸穿过绝缘层并接触硅晶片上的有源区的二极管开口。硅化钛层可以形成在二极管开口的内表面上并与活性区接触。二极管开口最初可以填充非晶硅插塞，其在沉积期间被掺杂并随后重结晶以形成大晶粒多晶硅。硅插头具有可以重掺杂第一类型掺杂剂的顶部部分和可以轻掺杂第二类型掺杂剂的底部部分。顶部可以由底部限定，以便不与硅化钛层接触。在垂直二极管结构的一个实施例中，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

5. 发明授权

US07547935B2 Semiconductor devices including buried digit lines that are laterally offset from corresponding active-device regions 有权
标题翻译：半导体器件包括从相应的有源器件区域横向偏移的埋置数字线
公开(公告)号：US07547935B2
公开(公告)日：2009-06-16
申请号：US10920938
申请日：2004-08-17
申请人： Tyler A. Lowrey
发明人： Tyler A. Lowrey
IPC分类号： H01L29/76 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/76838 , H01L27/105 , H01L27/1052 , H01L27/10811 , H01L27/10885 , H01L27/10888
摘要： A method of electrically linking contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corresponding digit line and, therefore, protrudes somewhat over a surface of the semiconductor device. A layer of insulative material is disposed over the semiconductor device with the mask material being exposed therethrough. The mask material is then removed, leaving open cavities that include the trench and a strap region continuous with the trench and with a connect region of the corresponding digit line. Conductive material is disposed within the cavity and electrically isolated from conductive material disposed in adjacent cavities, which define conductive plugs or studs and conductive straps from the conductive material. These plugs or studs and straps provide an electrically conductive link between each contact of the semiconductor device and its corresponding digit line. Semiconductor devices that include features that have been fabricated in accordance with the method of the present invention are also within the scope of the present invention.
摘要翻译：一种将半导体器件的触点电连接到其对应的数字线的方法。该方法包括将一定量的掩模材料设置在暴露于触点的沟槽中。掩模还邻接相应数字线的导电元件的连接区域，因此在半导体器件的表面上略微突出。绝缘材料层设置在半导体器件上，掩模材料暴露在其中。然后去除掩模材料，留下包括沟槽的开放空腔和与沟槽连续的带区域以及相应数字线的连接区域。导电材料设置在空腔内并与设置在相邻空腔中的导电材料电绝缘，其从导电材料限定导电塞或螺栓和导电带。这些插头或螺柱和带在半导体器件的每个触点与其对应的数字线之间提供导电连接。包括根据本发明的方法制造的特征的半导体器件也在本发明的范围内。

6. 发明授权

US07319057B2 Phase change material memory device 有权
标题翻译：相变材料存储器件
公开(公告)号：US07319057B2
公开(公告)日：2008-01-15
申请号：US10020757
申请日：2001-10-30
申请人： Tyler A. Lowrey
发明人： Tyler A. Lowrey
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/124 , H01L45/1253 , H01L45/1293 , H01L45/144 , H01L45/1691
摘要： A lower electrode may be covered by a protective film to reduce the exposure of the lower electrode to subsequent processing steps or the open environment. As a result, materials that may have advantageous properties as lower electrodes may be utilized despite the fact that they may be sensitive to subsequent processing steps or the open environment.
摘要翻译：下电极可以被保护膜覆盖，以减少下电极对后续处理步骤或开放环境的暴露。结果，可以使用可能具有作为下电极的有利特性的材料，尽管它们可能对随后的加工步骤或开放环境敏感。

7. 发明授权

US07247876B2 Three dimensional programmable device and method for fabricating the same 有权
标题翻译：三维可编程装置及其制造方法
公开(公告)号：US07247876B2
公开(公告)日：2007-07-24
申请号：US10231974
申请日：2002-08-30
申请人： Tyler A. Lowrey
发明人： Tyler A. Lowrey
IPC分类号： H01L47/00 , H01L29/06 , H01L31/00
CPC分类号： G11C13/0004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L29/16 , H01L29/861 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A three-dimensional memory device having polycrystalline silicon diode isolation elements for phase change memory cells and method for fabricating the same. The memory device includes a plurality of stacked memory cells to form a three-dimensional memory array. The polycrystalline silicon diode element selects the phase change memory cell. The memory device is fabricated by forming a plurality of phase change memory cells and diode isolation elements on a base layer. Additional layers of memory cells and isolation elements are formed over the initial layer.
摘要翻译：一种具有用于相变存储单元的多晶硅二极管隔离元件的三维存储器件及其制造方法。存储器件包括多个层叠的存储器单元以形成三维存储器阵列。多晶硅二极管元件选择相变存储单元。存储器件通过在基极层上形成多个相变存储器单元和二极管隔离元件来制造。存储单元和隔离元件的附加层在初始层上形成。

8. 发明授权

US07223688B2 Single level metal memory cell using chalcogenide cladding 有权
标题翻译：使用硫族化物包层的单层金属存储单元
公开(公告)号：US07223688B2
公开(公告)日：2007-05-29
申请号：US10389114
申请日：2003-03-14
申请人： Tyler A. Lowrey , Manzur Gill
发明人： Tyler A. Lowrey , Manzur Gill
IPC分类号： H01L21/3205
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.
摘要翻译：一种包括设置在基板上的第一导体和第二导体之间的相变材料体积的装置，以及耦合到所述体积的相变材料和所述第一导体的多个电极。一种方法，包括在衬底上的第一导体上引入耦合到所述第一导体的多个电极，在所述多个电极上引入相变材料并与所述多个电极电连通，以及将第二导体相变材料并耦合到相变材料。

9. 发明授权

US07166875B2 Vertical diode structures 有权
标题翻译：垂直二极管结构
公开(公告)号：US07166875B2
公开(公告)日：2007-01-23
申请号：US10804477
申请日：2004-03-19
申请人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
发明人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
IPC分类号： H01L29/24 , H01L29/861 , H01L29/88
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L27/0814 , H01L27/101 , H01L27/1021 , H01L27/24 , H01L29/6609 , H01L29/66136 , H01L29/861 , H01L45/04 , H01L45/145 , Y10S257/903 , Y10S257/91 , Y10S438/979
摘要： A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
摘要翻译：提供了一种制造垂直二极管的方法，所述垂直二氧化物具有与其相连的二极管开口，其延伸穿过绝缘层并接触硅晶片上的有源区。硅化钛层覆盖二极管开口的内表面并接触有源区。二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。顶部由底部界定，以便不与硅化钛层接触。对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

10. 发明授权

US06903010B2 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer 失效
标题翻译：具有硅化钛界面的硅的低电阻接触和无定形氮化钛氮化硼阻挡层
公开(公告)号：US06903010B2
公开(公告)日：2005-06-07
申请号：US10637427
申请日：2003-08-08
申请人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
发明人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
IPC分类号： C23C16/34 , H01L21/285 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76855 , C23C16/34 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76862
摘要： A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through a dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.
摘要翻译：提供了一种接触结构，其结合使用四 - 二烷基酰氨基 - 钛，Ti（NMe 2 O 3）4 Si 3 O 4的低压化学气相沉积（LPCVD）形成的无定形氮化钛阻挡层。，作为前体。通过将通过电介质层的接触开口蚀刻到要进行电接触的扩散区域来制造接触结构。钛金属沉积在晶片的表面上，使得扩散区域的暴露表面完全被金属层覆盖。钛金属层的至少一部分最终被转化为硅化钛，从而在扩散区的表面提供优异的导电界面。然后使用LPCVD工艺沉积氮化钛阻挡层，涂覆接触开口的壁和底板。以下是多晶硅或金属的化学气相沉积。

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