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    • 52. 发明授权
    • Using a data cache array as a DRAM load/store buffer
    • 使用数据高速缓存阵列作为DRAM加载/存储缓冲区
    • US08234478B1
    • 2012-07-31
    • US12256400
    • 2008-10-22
    • James RobertsDavid B. GlascoPatrick R. MarchandPeter B. HolmqvistGeorge R. LynchJohn H. Edmondson
    • James RobertsDavid B. GlascoPatrick R. MarchandPeter B. HolmqvistGeorge R. LynchJohn H. Edmondson
    • G06F12/00G06F13/00G06F13/28
    • G06F12/0895
    • One embodiment of the invention sets forth a mechanism for using the L2 cache as a buffer for data associated with read/write commands that are processed by the frame buffer logic. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves necessary cache lines for the read/write operations and transmits read commands to the frame buffer logic for processing. A data slice scheduler transmits a dirty data notification to the frame buffer logic when data associated with a write command is stored in an SRAM bank. The data slice scheduler schedules accesses to the SRAM banks and gives priority to accesses requested by the frame buffer logic to store or retrieve data associated with read/write commands. This feature allows cache lines reserved for read/write commands that are processed by the frame buffer logic to be made available at the earliest clock cycle.
    • 本发明的一个实施例提出了一种使用L2高速缓存作为与由帧缓冲器逻辑处理的读/写命令相关联的数据的缓冲器的机制。 标签查找单元跟踪L2高速缓存中每个高速缓存行的可用性,为读/写操作预留必要的高速缓存行,并将读命令发送到帧缓冲器逻辑进行处理。 当与写命令相关联的数据被存储在SRAM存储体中时,数据片调度器将脏数据通知发送到帧缓冲器逻辑。 数据片调度器调度对SRAM组的访问,并且优先级由帧缓冲器逻辑请求的访问来存储或检索与读/写命令相关联的数据。 该功能允许由帧缓冲器逻辑处理的读/写命令保留的高速缓存行在最早的时钟周期内可用。