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51. 发明授权

US09197402B2 Re-circulating time-to-digital converter (TDC) 有权
标题翻译：再循环时间数字转换器（TDC）
公开(公告)号：US09197402B2
公开(公告)日：2015-11-24
申请号：US13997229
申请日：2012-04-10
申请人： Hyung Seok Kim , Ashoke Ravi , William Y. Li , Kailash Chandrashekar
发明人： Hyung Seok Kim , Ashoke Ravi , William Y. Li , Kailash Chandrashekar
IPC分类号： H03M1/48 , H04L7/033 , H03L7/197 , G04F10/00
CPC分类号： H04L7/0331 , G04F10/005 , H03L7/1974
摘要： A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator. The TDC post-process module can generate a TDC output, which can be a binary representation of a phase difference between a reference signal and a VCO signal.
摘要翻译：再循环时间 - 数字转换器（TDC）可以包括触发参考环形振荡器（TRRO）和延迟模块。触发的参考环形振荡器可以在由参考信号边沿触发时产生周期性环形振荡器信号，其环路振荡器周期是压控振荡器（VCO）周期的选定比率。延迟模块可以在多个锁存器中存储由周期性环形振荡器信号对接的VCO信号的采样。每个锁存器可以产生采样的输出，并且每个锁存器输出可以表示VCO信号和TRRO信号之间的时差极性。在另一示例中，再循环TDC可以包括触发的参考环形振荡器，数字频率锁定模块和TDC后处理模块。数字频率锁定模块可以产生环形振荡器控制信号，为触发的参考环形振荡器设置环形振荡器周期。 TDC后处理模块可以产生TDC输出，其可以是参考信号和VCO信号之间的相位差的二进制表示。

52. 发明申请

US20150074156A1 METHODS AND SYSTEMS TO COMPENSATE FOR NON-LINEARITY OF A STOCHASTIC SYSTEM 有权
标题翻译：补偿系统非线性的方法和系统
公开(公告)号：US20150074156A1
公开(公告)日：2015-03-12
申请号：US14022683
申请日：2013-09-10
申请人： Ofir Degani , Ashoke Ravi , Hasnain Lakdawala
发明人： Ofir Degani , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： G06F5/00 , G06F17/18
CPC分类号： G06F5/00 , G04F10/005 , H03L7/085 , H03L2207/50 , H03M1/1014 , H03M1/1033
摘要： Determination of digital compensation to compensate for non-linearity of stochastic system configured to sample a phase difference, based on statistical analysis of calibration data generated by the stochastic system in response to a linear phase ramp. The stochastic system may include a set of stochastic sampler circuits to sample a phase difference at periodic events, and calibration data may include a digital value of set of stochastic samples for each of multiple events. The calibration data may include sequences of the digital values in which the digital values increment over a range of the stochastic system (i.e., between saturation states of the stochastic system). Statistical analysis may include histogram analysis to estimate the probability distribution of the calibration data. The stochastic system may be configured as part of a time-to-digital converter, which may be configured within a feedback loop of a digitally controllable phase lock loop.
摘要翻译：基于随机系统响应于线性相位斜坡生成的校准数据的统计分析，确定数字补偿以补偿配置为采样相位差的随机系统的非线性。随机系统可以包括一组随机采样器电路，以在周期性事件中采样相位差，并且校准数据可以包括多个事件中的每一个的随机样本集合的数字值。校准数据可以包括数字值的序列，其中数字值在随机系统的范围（即，随机系统的饱和状态之间）增加。统计分析可以包括直方图分析来估计校准数据的概率分布。随机系统可以被配置为时间 - 数字转换器的一部分，其可以配置在数字可控锁相环的反馈回路内。

53. 发明授权

US08390349B1 Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter 有权
标题翻译：次皮秒分辨率分段重新循环随机时间 - 数字转换器
公开(公告)号：US08390349B1
公开(公告)日：2013-03-05
申请号：US13533341
申请日：2012-06-26
申请人： Ashoke Ravi , Ofir Degani , Hyung Seok Kim , Hasnain Lakdawala , Yee W. Li , Paolo Madoglio
发明人： Ashoke Ravi , Ofir Degani , Hyung Seok Kim , Hasnain Lakdawala , Yee W. Li , Paolo Madoglio
IPC分类号： H03L7/06
CPC分类号： G04F10/005 , H03L2207/50
摘要： Disclosed is a method and apparatus to extend TDC resolution to better than 1 ps without incurring a matching and power penalty. Higher resolution can be achieved by segmenting the resolution between a mismatch free re-circulating time-to-digital converter (RTDC) and a stochastic time-to-digital converter (STDC). The disclosed RTDC replicates the same delay element to eliminate mismatch with the required dynamic range (200 ps for a 5 GHz example) and moderate resolution (3-5 ps typical corresponding to 6-7 bits for the 5 GHz case). While the STDC can achieve a resolution of 50 fs but with a range of only 3-5 ps which also corresponds to approximately 6-7 additional bits by exploiting process variations and mismatch to achieve a very fine resolution with limited dynamic range.
摘要翻译：公开了一种将TDC分辨率提高到1ps而不引起匹配和功率损失的方法和装置。可以通过在不匹配的循环时间数字转换器（RTDC）和随机时间 - 数字转换器（STDC）之间分辨分辨率来实现更高的分辨率。所公开的RTDC复制相同的延迟元件以消除与所需动态范围（对于5GHz示例为200ps）和中等分辨率（3-5ps典型对应于5GHz情况下的6-7位）的失配。虽然STDC可以实现50 fs的分辨率，但只有3-5 ps的范围，这也通过利用过程变化和失配来对应于大约6-7个附加位，以获得有限动态范围的非常精细的分辨率。

54. 发明申请

US20120049914A1 DYNAMIC ELEMENT MATCHING FOR TIME-TO-DIGITAL CONVERTERS 有权
标题翻译：用于时间到数字转换器的动态元件匹配
公开(公告)号：US20120049914A1
公开(公告)日：2012-03-01
申请号：US12872993
申请日：2010-08-31
申请人： Stefano Pellerano , Paolo Madoglio , Ashoke Ravi
发明人： Stefano Pellerano , Paolo Madoglio , Ashoke Ravi
IPC分类号： H03L7/06
CPC分类号： H03L7/1974 , H03L2207/50
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to dynamic element matching for time-to-digital converters. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与时间 - 数字转换器的动态元件匹配相关的方法，系统和装置。可以描述和要求保护其他实施例。

55. 发明授权

US07786914B2 Time-interleaved delta-sigma modulator 有权
标题翻译：时间交织的delta-sigma调制器
公开(公告)号：US07786914B2
公开(公告)日：2010-08-31
申请号：US12345524
申请日：2008-12-29
申请人： Paolo Madoglio , Ashoke Ravi
发明人： Paolo Madoglio , Ashoke Ravi
IPC分类号： H03M3/00
CPC分类号： H03M7/3004 , H03M7/3022
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to a time-interleaved delta-sigma modulator are described. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与时间交织的Δ-Σ调制器有关的方法，系统和装置。可以描述和要求保护其他实施例。

56. 发明授权

US07773669B2 Cascaded phase pulse position and pulse width modulation based digital transmitter 有权
标题翻译：级联相位脉冲位置和基于脉宽调制的数字发射器
公开(公告)号：US07773669B2
公开(公告)日：2010-08-10
申请号：US11837043
申请日：2007-08-10
申请人： Ofir Degani , Hasnain Lakdawala , Ashoke Ravi
发明人： Ofir Degani , Hasnain Lakdawala , Ashoke Ravi
IPC分类号： H03K7/04
CPC分类号： H04L25/4902
摘要： Briefly, in accordance with one or more embodiments, a digital transmitter may comprise two or more phase modulators in a cascaded arrangement. The phase modulators may modulate a local oscillator signal using control signals derived from the quadrature baseband data to be transmitted. A closed loop power control feedback arrangement may be used to compare the output power of the transmitter with a desired output signal, and make corrections to the output signal by modifying at least one of the control signals provided to the cascaded phase modulators.
摘要翻译：简而言之，根据一个或多个实施例，数字发射机可以包括两个或更多个级联布置的相位调制器。相位调制器可以使用从要发送的正交基带数据导出的控制信号来调制本地振荡器信号。可以使用闭环功率控制反馈装置来将发射机的输出功率与期望的输出信号进行比较，并且通过修改提供给级联相位调制器的控制信号中的至少一个来对输出信号进行校正。

57. 发明授权

US07710295B2 Inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling 有权
标题翻译：基于逆变器的归零（RZ）+非RZ（NRZ）信号
公开(公告)号：US07710295B2
公开(公告)日：2010-05-04
申请号：US11644348
申请日：2006-12-22
申请人： Dinesh Somasekhar , Sourav Saha , Gregory E. Ruhl , Ashoke Ravi
发明人： Dinesh Somasekhar , Sourav Saha , Gregory E. Ruhl , Ashoke Ravi
IPC分类号： H03M5/16
CPC分类号： H04B10/5162
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling. The interface circuit contains multiple ganged drivers (some or all of them are turned on at one point of time) and edge detection circuitry (to configure/modulate edges of the input data signal). These two circuits together generate weighted return-to-zero (RZ)+non-RZ (NRZ) signal.
摘要翻译：本发明的实施例一般涉及用于基于逆归零（RZ）+非RZ（NRZ）信令的基于逆变器的系统，方法和装置。接口电路包含多个组合的驱动器（其中一些或全部在一个时间点打开）和边沿检测电路（以配置/调制输入数据信号的边沿）。这两个电路一起产生加权归零（RZ）+非RZ（NRZ）信号。

58. 发明申请

US20100033257A1 PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT 有权
标题翻译：相位噪声最小相位/频率锁定电压控制振荡器电路
公开(公告)号：US20100033257A1
公开(公告)日：2010-02-11
申请号：US12579149
申请日：2009-10-14
申请人： Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
发明人： Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L7/0995 , H03L7/18 , H03L2207/06
摘要： A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.
摘要翻译：公开了一种用于嵌入在反馈系统中的压控振荡器（VCO）电路中的相位噪声最小化电路。相位噪声最小化电路包括噪声功率计，用于分析由反馈系统馈送到VCO的控制电压并确定其电压噪声功率。由于VCO由反馈系统控制，所以控制电压噪声功率也是在反馈系统的带宽内偏移的频率的VCO相位噪声功率的指示。 VCO具有几个参数，可以调整以影响其相位噪声。最小化算法生成最小化控制电压噪声功率（从而使VCO相位噪声功率）最小化的最佳参数集，并将其发送到振荡器。相位噪声最小化电路可以用于各种应用中，特别是在锁相环和锁相环VCO中。

59. 发明申请

US20090036064A1 DIGITAL INTEGRATED TRANSMITTER BASED ON FOUR-PATH PHASE MODULATION 审中-公开
标题翻译：基于四路相位调制的数字集成发射机
公开(公告)号：US20090036064A1
公开(公告)日：2009-02-05
申请号：US11831017
申请日：2007-07-31
申请人： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala
发明人： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala
IPC分类号： H04B1/40 , H04L27/20
CPC分类号： H03C3/40
摘要： Briefly, in accordance with one or more embodiments, a transmitter comprises four phase modulators to provide four path phase modulation. The phase modulators modulate local oscillator signals with control signals derived from quadrature baseband data to be transmitted to result in four phase modulated signals. The four phase modulated signals may be combined to provide a pulse position and pulse width modulated signal that may have a constant, or nearly constant, amplitude. The frequency spectrum of the control signals have narrower bandwidths and greater out of band attenuation resulting in higher suppression of out of channel and out of band noise.
摘要翻译：简而言之，根据一个或多个实施例，发射机包括四个相位调制器以提供四路径相位调制。相位调制器用来自正交基带数据的控制信号调制本地振荡器信号，以传输四个相位调制信号。可以组合四个相位调制信号以提供可以具有恒定或接近恒定幅度的脉冲位置和脉宽调制信号。控制信号的频谱具有较窄的带宽和较大的带外衰减，从而导致通道和带外噪声的更高的抑制。

60. 发明申请

US20080284530A1 PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT 审中-公开
标题翻译：相位噪声最小相位/频率锁定电压控制振荡器电路
公开(公告)号：US20080284530A1
公开(公告)日：2008-11-20
申请号：US11747927
申请日：2007-05-14
申请人： Stefano PELLERANO , Ashoke Ravi , Yorgos Palaskas
发明人： Stefano PELLERANO , Ashoke Ravi , Yorgos Palaskas
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03L7/0995 , H03L7/18 , H03L2207/06
摘要： A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.
摘要翻译：公开了一种用于嵌入在反馈系统中的压控振荡器（VCO）电路中的相位噪声最小化电路。相位噪声最小化电路包括噪声功率计，用于分析由反馈系统馈送到VCO的控制电压并确定其电压噪声功率。由于VCO由反馈系统控制，所以控制电压噪声功率也是在反馈系统的带宽内偏移的频率的VCO相位噪声功率的指示。 VCO具有几个参数，可以调整以影响其相位噪声。最小化算法生成最小化控制电压噪声功率（从而使VCO相位噪声功率）最小化的最佳参数集，并将其发送到振荡器。相位噪声最小化电路可以用于各种应用中，特别是在锁相环和锁相环VCO中。

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