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1. 发明授权

US07907018B2 Phase noise minimized phase/frequency-locked voltage-controlled oscillator circuit 有权
标题翻译：相位噪声最小相/锁频压控振荡电路
公开(公告)号：US07907018B2
公开(公告)日：2011-03-15
申请号：US12579149
申请日：2009-10-14
申请人： Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
发明人： Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03L7/0995 , H03L7/18 , H03L2207/06
摘要： A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.
摘要翻译：公开了一种用于嵌入在反馈系统中的压控振荡器（VCO）电路中的相位噪声最小化电路。相位噪声最小化电路包括噪声功率计，用于分析由反馈系统馈送到VCO的控制电压并确定其电压噪声功率。由于VCO由反馈系统控制，所以控制电压噪声功率也是在反馈系统的带宽内偏移的频率的VCO相位噪声功率的指示。 VCO具有几个参数，可以调整以影响其相位噪声。最小化算法生成最小化控制电压噪声功率（从而使VCO相位噪声功率）最小化的最佳参数集，并将其发送到振荡器。相位噪声最小化电路可以用于各种应用中，特别是在锁相环和锁相环VCO中。

2. 发明申请

US20100033257A1 PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT 有权
标题翻译：相位噪声最小相位/频率锁定电压控制振荡器电路
公开(公告)号：US20100033257A1
公开(公告)日：2010-02-11
申请号：US12579149
申请日：2009-10-14
申请人： Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
发明人： Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L7/0995 , H03L7/18 , H03L2207/06
摘要： A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.
摘要翻译：公开了一种用于嵌入在反馈系统中的压控振荡器（VCO）电路中的相位噪声最小化电路。相位噪声最小化电路包括噪声功率计，用于分析由反馈系统馈送到VCO的控制电压并确定其电压噪声功率。由于VCO由反馈系统控制，所以控制电压噪声功率也是在反馈系统的带宽内偏移的频率的VCO相位噪声功率的指示。 VCO具有几个参数，可以调整以影响其相位噪声。最小化算法生成最小化控制电压噪声功率（从而使VCO相位噪声功率）最小化的最佳参数集，并将其发送到振荡器。相位噪声最小化电路可以用于各种应用中，特别是在锁相环和锁相环VCO中。

3. 发明申请

US20080284530A1 PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT 审中-公开
标题翻译：相位噪声最小相位/频率锁定电压控制振荡器电路
公开(公告)号：US20080284530A1
公开(公告)日：2008-11-20
申请号：US11747927
申请日：2007-05-14
申请人： Stefano PELLERANO , Ashoke Ravi , Yorgos Palaskas
发明人： Stefano PELLERANO , Ashoke Ravi , Yorgos Palaskas
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03L7/0995 , H03L7/18 , H03L2207/06
摘要： A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.
摘要翻译：公开了一种用于嵌入在反馈系统中的压控振荡器（VCO）电路中的相位噪声最小化电路。相位噪声最小化电路包括噪声功率计，用于分析由反馈系统馈送到VCO的控制电压并确定其电压噪声功率。由于VCO由反馈系统控制，所以控制电压噪声功率也是在反馈系统的带宽内偏移的频率的VCO相位噪声功率的指示。 VCO具有几个参数，可以调整以影响其相位噪声。最小化算法生成最小化控制电压噪声功率（从而使VCO相位噪声功率）最小化的最佳参数集，并将其发送到振荡器。相位噪声最小化电路可以用于各种应用中，特别是在锁相环和锁相环VCO中。

4. 发明授权

US07729445B2 Digital outphasing transmitter architecture 有权
标题翻译：数字异相发射机架构
公开(公告)号：US07729445B2
公开(公告)日：2010-06-01
申请号：US11528812
申请日：2006-09-27
申请人： Ashoke Ravi , Mostafa A. Elmala , Richard B. Nicholls , Yorgos Palaskas , Krishnamurthy Soumyanath , Dinesh Somasekhar
发明人： Ashoke Ravi , Mostafa A. Elmala , Richard B. Nicholls , Yorgos Palaskas , Krishnamurthy Soumyanath , Dinesh Somasekhar
IPC分类号： H04K1/02
CPC分类号： H04L27/361 , H03F1/0294 , H03F3/211 , H03F3/245 , H04L27/368
摘要： Architectures including digital outphasing transmitters. Digital signal generation circuitry generates at least two base-band sinusoid signals. Bandpass modulation circuitry is coupled to receive the base-band sinusoid signals and generates at least two modulated digital signals. Power amplifiers are coupled to receive the modulated digital signals to amplify the modulated digital signals. The amplified modulated signals are combined and transmitted.
摘要翻译：架构包括数字异相变送器。数字信号产生电路产生至少两个基带正弦信号。带通调制电路被耦合以接收基带正弦信号并产生至少两个调制的数字信号。功率放大器被耦合以接收经调制的数字信号以放大调制的数字信号。放大的调制信号被组合并传输。

5. 发明申请

US20080075194A1 Digital outphasing transmitter architecture 有权
标题翻译：数字异相发射机架构
公开(公告)号：US20080075194A1
公开(公告)日：2008-03-27
申请号：US11528812
申请日：2006-09-27
申请人： Ashoke Ravi , Mostafa A. Elmala , Richard B. Nicholls , Yorgos Palaskas , Krishnamurthy Soumyanath , Dinesh Somasekhar
发明人： Ashoke Ravi , Mostafa A. Elmala , Richard B. Nicholls , Yorgos Palaskas , Krishnamurthy Soumyanath , Dinesh Somasekhar
IPC分类号： H04L25/49
CPC分类号： H04L27/361 , H03F1/0294 , H03F3/211 , H03F3/245 , H04L27/368
摘要： Architectures including digital outphasing transmitters.
摘要翻译：架构包括数字异相变送器。

6. 发明申请

US20090034603A1 SUBRANGING FOR A PULSE POSITION AND PULSE WIDTH MODULATION BASED TRANSMITTER 有权
标题翻译：用于脉冲位置和脉冲宽度调制的发射机的SUBRANGING
公开(公告)号：US20090034603A1
公开(公告)日：2009-02-05
申请号：US12176646
申请日：2008-07-21
申请人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Itshak Hod , Yorgos Palaskas , Masoud Sajadieh
发明人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Itshak Hod , Yorgos Palaskas , Masoud Sajadieh
IPC分类号： H03K7/08
CPC分类号： H03K7/10 , H03F3/2178 , H04B1/0483 , H04L25/4902
摘要： Briefly, in accordance with one or more embodiments, in a pulse position and pulse position modulation out-phasing transmitter, the range of the phase angle, theta, may be divided into more than one range to drive a first power amplifier with a first range of theta, and to drive a second power amplifier with a second range of theta. In one or more embodiments, a main power amplifier is driven with a first phase range having a higher probability density function, and an overload power amplifier is driven with a first phase range having a lower probability density function. In one or more embodiments, a full adder may be used to combine the two phases wherein the sum signal is used to drive the main power amplifier, and the carry signal is used to drive the overload power amplifier.
摘要翻译：简而言之，根据一个或多个实施例，在脉冲位置和脉冲位置调制输出相位变送器中，相位角θ的范围可被划分成多于一个范围以驱动具有第一范围的第一功率放大器的θ，并驱动具有θ的第二范围的第二功率放大器。在一个或多个实施例中，主功率放大器由具有较高概率密度函数的第一相位范围驱动，而过载功率放大器由具有较低概率密度函数的第一相位范围驱动。在一个或多个实施例中，全加器可以用于组合两相，其中求和信号用于驱动主功率放大器，并且进位信号用于驱动过载功率放大器。

7. 发明授权

US08098726B2 Subranging for a pulse position and pulse width modulation based transmitter 有权
标题翻译：基于脉冲位置和基于脉宽调制的发射机的分组
公开(公告)号：US08098726B2
公开(公告)日：2012-01-17
申请号：US12176646
申请日：2008-07-21
申请人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Itshak Hod , Yorgos Palaskas , Masoud Sajadieh
发明人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Itshak Hod , Yorgos Palaskas , Masoud Sajadieh
IPC分类号： H03K7/08
CPC分类号： H03K7/10 , H03F3/2178 , H04B1/0483 , H04L25/4902
摘要： Briefly, in accordance with one or more embodiments, in a pulse position and pulse position modulation out-phasing transmitter, the range of the phase angle, theta, may be divided into more than one range to drive a first power amplifier with a first range of theta, and to drive a second power amplifier with a second range of theta. In one or more embodiments, a main power amplifier is driven with a first phase range having a higher probability density function, and an overload power amplifier is driven with a first phase range having a lower probability density function. In one or more embodiments, a full adder may be used to combine the two phases wherein the sum signal is used to drive the main power amplifier, and the carry signal is used to drive the overload power amplifier.
摘要翻译：简而言之，根据一个或多个实施例，在脉冲位置和脉冲位置调制输出相位变送器中，相位角θ的范围可被划分成多于一个范围以驱动具有第一范围的第一功率放大器的θ，并驱动具有θ的第二范围的第二功率放大器。在一个或多个实施例中，主功率放大器由具有较高概率密度函数的第一相位范围驱动，而过载功率放大器由具有较低概率密度函数的第一相位范围驱动。在一个或多个实施例中，全加器可以用于组合两相，其中求和信号用于驱动主功率放大器，并且进位信号用于驱动过载功率放大器。

8. 发明申请

US20080070512A1 Offset-frequency loop-back calibration 有权
标题翻译：偏移环回校准
公开(公告)号：US20080070512A1
公开(公告)日：2008-03-20
申请号：US11522599
申请日：2006-09-18
申请人： Georgios Palaskas , Stefano Pellerano , Ashoke Ravi
发明人： Georgios Palaskas , Stefano Pellerano , Ashoke Ravi
IPC分类号： H04B1/44
CPC分类号： H03F1/32 , H03F1/34 , H03F3/24 , H03F2200/321 , H03F2200/451 , H04B2001/0433
摘要： Embodiments of methods and means for calibrating a linearization characteristic within an RF transceiver system are provided. Such embodiments generally include extracting a portion of an output signal and frequency shifting or translating that signal by a predetermined value. The frequency shifted signal is then summed or otherwise introduced into a receiver signal pathway where it is analyzed by digital signal processing or other means to determine if linearization distortion is present. Linearization calibration of a power amplifier, a low-noise amplifier and/or other functionality within the system can then be performed in an automatic, reliable and ongoing manner.
摘要翻译：提供了用于校准RF收发器系统内的线性化特性的方法和装置的实施例。这样的实施例通常包括提取输出信号的一部分并将该信号频移或转换预定值。然后将频移信号相加或以其他方式引入到接收机信号路径中，其中通过数字信号处理或其他手段来分析，以确定是否存在线性化失真。然后可以以自动，可靠和持续的方式执行系统内的功率放大器，低噪声放大器和/或其他功能的线性化校准。

9. 发明申请

US20160374021A1 FULLY INTEGRATED WAKE-UP RECEIVER 审中-公开
标题翻译：完全集成的唤醒接收器
公开(公告)号：US20160374021A1
公开(公告)日：2016-12-22
申请号：US15164667
申请日：2016-05-25
申请人： Erkan Alpman , Ahmad B. Khairi , Stefano Pellerano , Ashoke Ravi
发明人： Erkan Alpman , Ahmad B. Khairi , Stefano Pellerano , Ashoke Ravi
IPC分类号： H04W52/02 , H04B1/30
CPC分类号： H04W52/0229 , Y02D70/00 , Y02D70/1224 , Y02D70/1262 , Y02D70/1264 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/162 , Y02D70/164 , Y02D70/166 , Y02D70/168 , Y02D70/21 , Y02D70/22 , Y02D70/26
摘要： An apparatus is provided which comprises: a mixer to mix a first signal of a first frequency with a second signal of a second frequency, and to generate a first output; a switched-capacitor multiplier, coupled to the mixer, to receive the first output and to provide a second output with reduced noise; and an amplifier, coupled to the switched-capacitor multiplier, to amplify the second output.
摘要翻译：提供了一种装置，其包括：混合器，用于混合第一频率的第一信号和第二频率的第二信号，并产生第一输出; 耦合到所述混频器的开关电容倍增器，以接收所述第一输出并提供具有降低的噪声的第二输出; 以及耦合到开关电容器乘法器的放大器，以放大第二输出。

10. 发明授权

US08198929B2 Dynamic element matching for time-to-digital converters 有权
标题翻译：时间 - 数字转换器的动态元件匹配
公开(公告)号：US08198929B2
公开(公告)日：2012-06-12
申请号：US12872993
申请日：2010-08-31
申请人： Stefano Pellerano , Paolo Madoglio , Ashoke Ravi
发明人： Stefano Pellerano , Paolo Madoglio , Ashoke Ravi
IPC分类号： H03L7/06
CPC分类号： H03L7/1974 , H03L2207/50
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to dynamic element matching for time-to-digital converters. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与时间 - 数字转换器的动态元件匹配相关的方法，系统和装置。可以描述和要求保护其他实施例。

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