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51. 发明授权

US07932157B2 Test structure formation in semiconductor processing 有权
标题翻译：半导体加工中测试结构的形成
公开(公告)号：US07932157B2
公开(公告)日：2011-04-26
申请号：US11772128
申请日：2007-06-30
申请人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
发明人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , G03F9/7046 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices.
摘要翻译：在半导体处理期间形成测试结构。测试结构允许在过程进行时监测性能特征。测试结构形成有一个单一的掩模，该掩模的使用方式也允许形成对准标记，这些对准标记在后续层次被图案化时不会相互干扰。使用掩模的方式也允许形成具有不同特征的不同类型的测试结构。不同类型的测试结构可以提供对不同类型设备的性能特征的洞察。

52. 发明授权

US07923305B1 Patterning method for high density pillar structures 有权
标题翻译：高密度柱结构图案化方法
公开(公告)号：US07923305B1
公开(公告)日：2011-04-12
申请号：US12686201
申请日：2010-01-12
申请人： Natalie Nguyen , Paul Wai Kie Poon , Steven J. Radigan , Michael Konevecki , Yung-Tin Chen
发明人： Natalie Nguyen , Paul Wai Kie Poon , Steven J. Radigan , Michael Konevecki , Yung-Tin Chen
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L21/0337 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1675
摘要： A method of making a device includes forming a first sacrificial layer over an underlying layer, forming a first photoresist layer over the first sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, etching the first sacrificial layer using both the first and the second photoresist features as a mask to form first sacrificial features, forming a spacer layer over the first sacrificial features, etching the spacer layer to form spacer features and to expose the sacrificial features, removing the first sacrificial features, and etching at least part of the underlying layer using the spacer features as a mask.
摘要翻译：制造器件的方法包括在下层上形成第一牺牲层，在第一牺牲层上形成第一光致抗蚀剂层，使第一光致抗蚀剂层形成图形以形成第一光致抗蚀剂特征，使第一光致抗蚀剂特征不溶于溶剂，形成在第一光致抗蚀剂特征上的第二光致抗蚀剂层，图案化第二光致抗蚀剂层以形成第二光致抗蚀剂特征，使用第一和第二光致抗蚀剂特征作为掩模蚀刻第一牺牲层以形成第一牺牲特征，第一牺牲特征，蚀刻间隔层以形成间隔物特征并暴露牺牲特征，去除第一牺牲特征，以及使用间隔物特征作为掩模来蚀刻至少部分下层。

53. 发明授权

US07786015B2 Method for fabricating self-aligned complementary pillar structures and wiring 有权
标题翻译：自对准互补柱结构和布线的制造方法
公开(公告)号：US07786015B2
公开(公告)日：2010-08-31
申请号：US12149151
申请日：2008-04-28
申请人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan , Christopher J. Petti , Steven Maxwell
发明人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan , Christopher J. Petti , Steven Maxwell
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , H01L27/1021
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔的特征，在所述至少两个特征上形成侧壁间隔物，选择性地去除间隔开的特征，用填料特征填充第一侧壁间隔物和第二侧壁间隔物之间的空间，选择性地去除侧壁间隔物以留下彼此间隔开的多个填料特征，并使用填料特征来蚀刻至少一个器件层，如一个面具

54. 发明申请

US20100167502A1 Nanoimprint enhanced resist spacer patterning method 有权
公开(公告)号：US20100167502A1
公开(公告)日：2010-07-01
申请号：US12318590
申请日：2008-12-31
申请人： Bing K. Yen , Chun-Ming Wang , Yung-Tin Chen , Steven Maxwell
发明人： Bing K. Yen , Chun-Ming Wang , Yung-Tin Chen , Steven Maxwell
IPC分类号： H01L21/36 , H01L21/467
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/3086 , H01L27/101 , H01L27/1021
摘要： A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask.

55. 发明申请

US20090269932A1 Method for fabricating self-aligned complimentary pillar structures and wiring 有权
标题翻译：自对准互补柱结构和布线的制造方法
公开(公告)号：US20090269932A1
公开(公告)日：2009-10-29
申请号：US12149151
申请日：2008-04-28
申请人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan , Christopher J. Petti , Steven Maxwell
发明人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan , Christopher J. Petti , Steven Maxwell
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , H01L27/1021
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔的特征，在所述至少两个特征上形成侧壁间隔物，选择性地去除间隔开的特征，用填料特征填充第一侧壁间隔物和第二侧壁间隔物之间的空间，选择性地去除侧壁间隔物以留下彼此间隔开的多个填料特征，并使用填料特征来蚀刻至少一个器件层，如一个面具

56. 发明申请

US20090001615A1 SEMICONDUCTOR TEST STRUCTURES 有权
标题翻译：半导体测试结构
公开(公告)号：US20090001615A1
公开(公告)日：2009-01-01
申请号：US11772130
申请日：2007-06-30
申请人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
发明人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L22/34 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.
摘要翻译：在半导体处理期间形成不同类型的测试结构。一种类型的测试结构包括彼此对准并且由不同层形成的特征。其他类型的测试结构包括由不同于其它测试结构特征的各层形成的特征。不同类型的测试结构形成有单个掩模，其以允许形成对准标记的方式使用，其中随后的层被图案化而不会彼此干扰。不同类型的测试结构可以随着半导体工艺的进行而深入了解不同类型器件的性能特征。

57. 发明申请

US20080160424A1 Hybrid mask and method of making same 有权
标题翻译：混合面膜及其制作方法
公开(公告)号：US20080160424A1
公开(公告)日：2008-07-03
申请号：US11648245
申请日：2006-12-29
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： G03F1/00
CPC分类号： G03F9/7076 , G03F1/36
摘要： A hybrid topography mask is designed for facilitating the fabrication of a semiconductor wafer. The hybrid mask includes a substrate having a light receiving surface. The light receiving surface defines a plane. Pluralities of pattern elements are etched into and out of the light receiving surface. Each of the plurality of pattern elements defines a pattern surface that is parallel to the light receiving surface. Pattern sides extend between the pattern elements and the light receiving surface. Each of the pattern sides extends perpendicularly between the light receiving surface and the pattern elements. The hybrid mask also includes a tapered sub-resolution assist element etched out of the light receiving surface to position the mask with respect to the semiconductor wafer. The tapered sub-resolution assist element is fabricated to avoid affecting any photoresist residue from the sub-resolution assist element's presence on the semiconductor wafer disposed adjacent the hybrid mask.
摘要翻译：混合地形掩模被设计用于促进半导体晶片的制造。混合掩模包括具有光接收表面的基板。光接收表面限定一个平面。多个图案元素被蚀刻入和射出光接收表面。多个图案元件中的每一个限定平行于光接收表面的图案表面。图案侧在图案元件和光接收表面之间延伸。每个图案侧在光接收表面和图案元件之间垂直地延伸。混合掩模还包括从光接收表面蚀刻出的锥形次分辨率辅助元件，以相对于半导体晶片定位掩模。制造锥形子分辨率辅助元件以避免影响副分辨率辅助元件在邻近混合掩模设置的半导体晶片上的存在的任何光致抗蚀剂残留物。

58. 发明授权

US07291562B2 Method to form topography in a deposited layer above a substrate 失效
标题翻译：在基材上方的沉积层中形成形貌的方法
公开(公告)号：US07291562B2
公开(公告)日：2007-11-06
申请号：US11298015
申请日：2005-12-09
申请人： Yung-Tin Chen , Samuel V Dunton
发明人： Yung-Tin Chen , Samuel V Dunton
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L21/3212 , H01L21/76819 , H01L21/8221 , H01L23/544 , H01L23/585 , H01L27/0688 , H01L27/1021 , H01L27/105 , H01L2223/54426 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In the present invention a dummy structure is formed in a first deposited layer in order to create topography, generally a raised area, in a deposited layer formed above and later than the first deposited layer. This topography may be advantageous in later steps. In one embodiment, transferred topography allows an alignment or overlay mark obscured by an opaque layer to be located by this enhanced topography. In another embodiment, a raised volume of dielectric material prevents features at the outside of an array area from being overpolished during a CMP step. This method may prove useful in other contexts as well. The size, shape, and placement of the dummy structure is tailored to form the desired excess volume.
摘要翻译：在本发明中，在第一沉积层中形成虚拟结构，以便在形成于第一沉积层之上和之后的沉积层中形成一般凸起区域的形貌。这种形态在后面的步骤中可能是有利的。在一个实施例中，转移的形貌允许由不透明层遮蔽的对准或覆盖标记由该增强的形貌定位。在另一个实施例中，凸起体积的介电材料防止阵列区域外部的特征在CMP步骤期间被过度抛光。这种方法也可能在其他情况下也是有用的。调整虚拟结构的大小，形状和位置以形成所需的过剩体积。

59. 发明公开

US20230147421A1 Three-Dimensional Ferroelectric Random-Access Memory (FeRAM) 审中-公开
公开(公告)号：US20230147421A1
公开(公告)日：2023-05-11
申请号：US17984164
申请日：2022-11-09
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： H10B51/20 , H01L29/66 , H01L29/78 , H10B51/30
CPC分类号： H01L27/11597 , H01L29/6684 , H01L29/78391 , H01L27/1159
摘要： A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

60. 发明授权

US08841648B2 Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same 有权
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：US08841648B2
公开(公告)日：2014-09-23
申请号：US12904802
申请日：2010-10-14
申请人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
发明人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24 , G11C13/00 , G11C11/56
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。提供了许多其他方面。

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