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    • 2. 发明授权
    • Method for reducing dielectric overetch using a dielectric etch stop at a planar surface
    • 在平坦表面使用电介质蚀刻停止来减少介电过程的方法
    • US07422985B2
    • 2008-09-09
    • US11090526
    • 2005-03-25
    • Samuel V DuntonChristopher J PettiUsha Raghuram
    • Samuel V DuntonChristopher J PettiUsha Raghuram
    • H01L21/302
    • H01L27/1021H01L21/76802H01L21/76829Y10S438/90
    • A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
    • 基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。 在优选实施例中,导电或半导体特征是形成垂直取向的二极管的柱。 不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。 选择性蚀刻蚀刻第二介电材料中的孔或沟槽,使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。 在优选实施例中,通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质,使氧化物凹陷,用第二电介质(例如氮化物)填充,然后平坦化以共存氮化物和导电或 半导体功能。